Image Processing Toolbox in Verilog using Basys3 FPGA
SPI master and SPI slave for FPGA written in VHDL
Support files for participating in a Fomu workshop
🎲 A Tiny and Platform-Independent True Random Number Generator for any ...
Basic RISC-V CPU implementation in VHDL.
Space Invaders game implemented with VHDL
PDP-11/70 CPU core and SoC
A bit-serial CPU written in VHDL, with a simulator written in C.
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface M...
VCD file (Value Change Dump) command line viewer
A VHDL frontend for Yosys
👇 Add capacitive touch buttons to any FPGA!
RTL implementation of components for DVB-S2
Implementations of the Simon and Speck Block Ciphers
:key: Technology-agnostic Physical Unclonable Function (PUF) hardware mo...