w11: PDP 11/70 CPU and SoC

Overview

The project contains the VHDL code for a complete DEC PDP-11 system: a PDP-11/70 CPU with a memory management unit, but without a floating point unit, a complete set of mass storage peripherals (RK11/RK05, RL11/RL02, RH70/RP06, TM11/TU10) and a rather complete set of UNIBUS peripherals (DL11, LP11, PC11, DZ11, and DEUNA), and last but not least a cache and memory controllers for SRAM, PSRAM and SDRAM (via Xilinx MIG core). The design is FPGA proven, runs currently on Digilent Arty A7, Basys3, Cmod A7, Nexys A7, Nexys4, Nexys3, Nexys2 and S3board boards and boots 5th Edition UNIX, 2.11BSD UNIX, as well as various DEC operating systems from provided oskits.

The current implementation forwards the IO requests from all devices via a fast serial connection to a backend server on a PC, which translates these requests and maps them to contemporary interfaces. True standalone systems are on the project roadmap.

For more information look into:

• w11 project home page, especially the sections on feature set and overall architecture.
• w11 project blog.
• change log and installation notes.
• guides to build bit files and test benches with Xilinx Vivado and Xilinx ISE.
• guides to run test benches and to boot operating systems.
• known issues.
• known differences.
• the impatient readers can try their luck with the quick start guide.

A short description of the directory layout is provided separately, the top-level directories are

Note on freecores/w11

The freecores team created in 2014 a copy of almost all OpenCores cores in Github under freecores. This created freecores/w11 which is outdated and not maintained. Only wfjm/w11 is maintained.

License

This project is released under the GPL V3 license, all files contain an SPDX-style disclaimer:

SPDX-License-Identifier: GPL-3.0-or-later

The full text of the GPL license is in this directory as License.txt.