AXI SystemVerilog Modules for High-Performance On-Chip Communication

This repository provides modules to build on-chip communication networks adhering to the AXI4 or AXI4-Lite standards. For high-performance communication, we implement AXI4+ATOPs from AXI5. For lightweight communication, we implement AXI4-Lite. We aim to provide a complete end-to-end communication platform, including endpoints such as DMA engines and on-chip memory controllers.

Our design goals are:

• Topology Independence: We provide elementary building blocks such as protocol multiplexers and demultiplexers that allow users to implement any network topology. We also provide commonly used interconnecting components such as a crossbar.
• Modularity: We favor design by composition over design by configuration where possible. We strive to apply the Unix philosophy to hardware: make each module do one thing well. This means you will more often instantiate our modules back-to-back than change a parameter value to build more specialized networks.
• Fit for Heterogeneous Networks: Our modules are parametrizable in terms of data width and transaction concurrency. This allows to create optimized networks for a wide range of performance (e.g., bandwidth, concurrency, timing), power, and area requirements. We provide modules such as data width converters and ID width converters that allow to join subnetworks with different properties, creating heterogeneous on-chip networks.
• Full AXI Standard Compliance.
• Compatibility with a wide range of (recent versions of) EDA tools and implementation in standardized synthesizable SystemVerilog.

The design and microarchitecture of the modules in this repository is described in this paper (preprint). If you use our work in your research, please cite it.

List of Modules

In addition to the documents linked in the following table, we are setting up documentation auto-generated from inline docstrings. (Replace master in that URL with a tag to get the documentation for a specific version.)

Synthesizable Verification Modules

The following modules are meant to be used for verification purposes only but are synthesizable to be used in FPGA environments.

Simulation-Only Modules

In addition to the modules above, which are available in synthesis and simulation, the following modules are available only in simulation. Those modules are widely used in our testbenches, but they are also suitable to build testbenches for AXI modules and systems outside this repository.

Atomic Operations

AXI4+ATOPs means the full AXI4 specification plus atomic operations (ATOPs) as defined in Section E1.1 of the AMBA 5 specification. This has the following implications for modules that do not implement ATOPs and systems that include such modules:

• Masters that do not issue ATOPs must set aw_atop to '0.
• Slaves that do not support ATOPs must specify this in their interface documentation and can ignore the aw_atop signal.
• System designers are responsible for ensuring that
  1. slaves that do not support ATOPs are behind an axi_atop_filter if any master could issue an ATOP to such slaves and
  2. the aw_atop signal is well-defined at the input of any (non-AXI4-Lite) module in this repository.

Masters and slaves that do support ATOPs must adhere to Section E1.1 of the AMBA 5 specification. In particular:

• ATOPs that have the aw_atop[axi_pkg::ATOP_R_RESP] bit set generate a write response (B channel) beat and at least one read response (R channel) beat. All modules for which the aw_atop[axi_pkg::ATOP_R_RESP] bit could be set at their master port must be able to handle both B and R beats (in any order and without requiring a simultaneous handshake) for each such ATOP request. All modules for which the aw_atop[axi_pkg::ATOP_R_RESP] bit could be set at their slave port must respond with the appropriate number of B and R beats for each such ATOP request.
• ATOPs must not use the same AXI ID as any other transaction that is outstanding at the same time.

Which EDA Tools Are Supported?

Our code is written in standard SystemVerilog (IEEE 1800-2012, to be precise), so the more important question is: Which subset of SystemVerilog does your EDA tool support?

We aim to be compatible with a wide range of EDA tools. For this reason, we strive to use as simple language constructs as possible, especially for our synthesizable modules. We encourage contributions that further simplify our code to make it compatible with even more EDA tools. We also welcome contributions that work around problems that specific EDA tools may have with our code, as long as:

• the EDA tool is reasonably widely used,
• recent versions of the EDA tool are affected,
• the workaround does not break functionality in other tools, and
• the workaround does not significantly complicate code or add maintenance overhead.

In addition, we suggest to report issues with the SystemVerilog language support directly to the EDA vendor. Our code is fully open and can / should be shared with the EDA vendor as a testcase for any language problem encountered.

All code in each release and on the default branch is tested on a recent version of at least one industry-standard RTL simulator and synthesizer. You can examine the CI settings to find out which version of which tool we are running.