Haskell to VHDL/Verilog/SystemVerilog compiler
Verible is a suite of SystemVerilog developer tools, including a parser,...
OpenLane is an automated RTL to GDSII flow based on several components i...
Send video/audio over HDMI on an FPGA
AXI SystemVerilog synthesizable IP modules and verification infrastructu...
An abstraction library for interfacing EDA tools
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branc...
SystemVerilog to Verilog conversion
An FPGA-based USB full-speed device core to implement USB-serial, USB-ca...
FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基...
Veryl: A Modern Hardware Description Language
SystemVerilog parser library fully compliant with IEEE 1800-2017
80186 compatible SystemVerilog CPU core and FPGA reference design
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simula...
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Pro...