CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Includes:
FPGA projects that use Logic utilities for creating, building and testing:
These 3rd party tools and libraries are required. They must be installed to build logic library:
These 3rd party tools and libraries are optional. They must be installed to build and run tests:
These 3rd party tools and libraries are optional:
Clone project repository:
git clone [email protected]:tymonx/logic.git
Change current location to project directory:
cd logic
Create build directory:
mkdir build
Change current location to build directory:
cd build
Create build scripts using CMake:
cmake ..
Build project using CMake (generic):
cmake --build . --target all
Or build project using make:
make -j`nproc`
It is much faster to recompile project using Ninja rather than Unix makefiles:
cmake -G Ninja ..
cmake --build . --target all
To build documentation:
cmake --build . target doc
Built HTML documentation can be found in:
doc/html
To view HTML documentation, open it using web browser:
<WEB_BROWSER> doc/html/index.html
Run all unit tests:
ctest
Run only unit tests for AXI4-Stream:
ctest -R axi4_stream
Waveforms from unit tests run under ModelSim are stored in:
modelsim/unit_tests/<unit_test_name>
Waveforms from unit tests run under Verilator are stored in:
verilator/unit_tests/<unit_test_name>
All unit tests logs are stored in:
Testing/Temporary/LastTest.log
Run Verilator coverage after running all tests:
cmake --build . --target verilator-coverage
Enable Verilator analysis:
add_hdl_source(<hdl-module-filename>
ANALYSIS
TRUE
)
Run Verilator analysis for <hdl-module-name>
:
make verilator-analysis-<hdl-module-name>
Run Verilator analysis for all HDL modules:
make verilator-analysis-all
Use add_quartus_project()
function to create Quartus project:
add_quartus_project(<top_level_entity>)
Quartus project will be created under:
quartus/<top_level_entity>
RTL analysis and elaboration in Intel FPGA Quartus
for top level entity:
cmake --build . --target quartus-analysis-<top_level_entity>
RTL compilation in Intel FPGA Quartus
for top level entity:
cmake --build . --target quartus-compile-<top_level_entity>
RTL analysis and elaboration in Intel FPGA Quartus
for all top level
entities:
cmake --build . --target quartus-analysis-all
RTL compilation in Intel FPGA Quartus
for all top level entities:
cmake --build . --target quartus-compile-all
Use add_vivado_project()
function to create Vivado project:
add_vivado_project(<top_level_entity>)
Vivado project will be created under:
vivado/<top_level_entity>
RTL analysis and elaboration in Xilinx Vivado
for top level entity:
cmake --build . --target vivado-analysis-<top_level_entity>
Change current location to another RTL project root directory:
cd <rtl_project_root_directory>
Clone and add logic repository to RTL project as git submodule:
git submodule add [email protected]:tymonx/logic.git
Add these lines to CMakeLists.txt root file:
set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH}
${CMAKE_CURRENT_LIST_DIR}/logic/cmake
)
include(AddLogic)
enable_testing()
add_subdirectory(logic)