Best 7 Modelsim Open Source Projects

Basic Verilog

Must-have verilog systemverilog modules

Edalize

An abstraction library for interfacing EDA tools

Logic

CMake, SystemVerilog and SystemC utilities for creating, building and te...

Hdl Checker

Repurposing existing HDL tools to help writing better code

FPGA Application Development And Simulation

《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的...

JSON For VHDL

A JSON library implemented in VHDL.

Vim Hdl

Vim plugin to aid VHDL development (for LSP, see https://github.com/suot...