VUnit is a unit testing framework for VHDL/SystemVerilog
Various HDL (Verilog) IP Cores
Python-based Hardware Design Processing Toolkit for Verilog HDL
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, B...
NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural ...
Veriloggen: A Mixed-Paradigm Hardware Construction Framework
A dual clock asynchronous FIFO written in verilog, tested with Icarus Ve...
High throughput JPEG decoder in Verilog for FPGA
Image Processing Toolbox in Verilog using Basys3 FPGA
A complete open-source design-for-testing (DFT) Solution
5-stage pipelined 32-bit MIPS microprocessor in Verilog
2017级北航计算机学院计算机组成原理课程设计(MIPS CPU)
System Verilog based Verification of MIPS 5 staged pipelined processor u...
A simple implementation of a UART modem in Verilog.
中山大学计算机组成原理实验 (2018 秋)：用 Verilog 设计并实现的简易单周期...