High throughput JPEG decoder in Verilog for FPGA
Github: https://github.com/ultraembedded/core_jpeg
This project is a JPEG decoder core for FPGA written in Verilog.
The current version of the JPEG decoder uses the following resources on a Xilinx 7 series FPGA (post-implementation);
The design is also able to meet timing >= 75MHz.
Peak JPEG decode performance is as follows;
The purpose of this design was to replace a 3rd party JPEG decoder core used in my Motion JPEG based FPGA video player.
Motion JPEG has worse compression performance than MPEG based video, but the complexity of the HW required is low enough that it can be used on low(-ish)-end FPGAs.
Video playback usually requires at least 25 frames per second, hence there is a budget of less than 40ms per JPEG frame.
This fact drives the design choices taken for this implementation.
Clearly, the higher the resolution, the more pixels that must be produced from the JPEG decoder within that 40ms budget, so this core is designed to have high throughput in the output stages - with additional resources dedicated to the IDCT transform, and output re-ordering stages to facilitate this.
The current release does not support;
Under the GNU Image Manipulation Program, the following 'X' options are not supported currently;
Note: Support for 'optimised' Huffman tables is possible when design parameter SUPPORT_WRITABLE_DHT=1.
This functionality increases the core size substantially and reduces performance.