An easily internationalizable, accessible, mobile-friendly datepicker li...
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus...
Code generation tool for control and status registers
🌒 Light and dark blog theme for Jekyll, inspired by Dash UI for Atom.
Recipe for FPGA cooking
Fast, Responsive, Multi Language, Both Direction Support and Configurabl...
odio is now Strimio!
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at htt...
Test suite designed to check compliance with the SystemVerilog standard.
Free RTL Bootstrap 3 Admin Template
CMake, SystemVerilog and SystemC utilities for creating, building and te...
Awesome Learning - Learn JavaScript and Front-End Fundamentals at your o...
FPGA-based USB fast data transmission using FT232H/FT600 chip. 使用FT232...
VeeR EL2 Core
Adds direction (LTR, RTL) variants to your Tailwind project