Salamandra is a tool to find spy microphones that use radio freq to tran...
VeeR EH1 core
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
:earth_africa: Map location picker component for Android. Based on Googl...
Various HDL (Verilog) IP Cores
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
Repository for basic (and not so basic) Verilog blocks with high re-use ...
A library which configures a divider for a RecyclerView.
Simple RISC-V 3-stage Pipeline in Chisel
An FPGA-based USB full-speed device core to implement USB-serial, USB-ca...
A curated list of awesome projects and dev/design resources for supporti...
RTL edition of bootstrap v4 for rtl languages like Farsi and Arabic
Veryl: A Modern Hardware Description Language
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simula...
An easily internationalizable, accessible, mobile-friendly datepicker li...