PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
Verilog implementation of the symmetric block cipher AES (Advanced Encry...
Reverse-engineered schematics for DMG-CPU-B
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector ...
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integ...
Code generation tool for control and status registers
CMake, SystemVerilog and SystemC utilities for creating, building and te...
Cryptocurrency ASIC mining hardware monitor using a simple web interface
A 256-RISC-V-core system with low-latency access into shared L1 memory.
SystemRDL 2.0 language compiler front-end
Awesome ASIC design verification
A dual clock asynchronous FIFO written in verilog, tested with Icarus Ve...
Tool to generate register RTL, models, and docs using SystemRDL or JSpec...
Hive OS client for ASICs
A seamless python to Cadence Virtuoso Skill interface