RVVM - The RISC-V Virtual Machine

RISC-V CPU & System software implementation written in С

What's working

• Passes RISC-V compliance/torture tests for both RV64 & RV32
• OpenSBI, U-Boot, custom firmwares boot and execute properly
• Working Linux, FreeBSD, OpenBSD, Haiku & other cool OSes
• Tracing JIT, multicore support
• Framebuffer display, mouse & keyboard, UART shell
• NVMe storage drives
• Networking

💡 Tell me more...

• Feature-complete RV64IMAFDC instruction set
• Multicore support (SMP), SV32/SV39/SV48/SV57 MMU
• Tracing RVJIT with x86_64, ARM64, RISC-V, i386, ARM backends (faster than QEMU, yay!)
• Bootrom, Kernel Image loading, ELF support
• Device Tree auto-generation, passing to firmware/kernel
• RVVM Public API for VM integration
• UART 16550a-compatible text console
• PLIC/ACLINT, Timers, Poweroff/reset
• Generic PCI Express Bus
• NVMe storage, image TRIM support, fast IO
• Framebuffer display, GUI for X11/WinAPI/Haiku/SDL
• I2C HID keyboard & mouse, OpenCores I2C controller
• Realtek RTL8169, OpenCores Ethernet NICs
• Userspace networking
• VFIO PCI Passthrough (For GPUs, etc)
• SiFive GPIO
• Deprecated: PS2 keyboard & mouse, ATA (IDE) drive, Linux TAP

📦 Installing

🛠 Building

Currently builds using GNU Make (recommended) or CMake and is extremely portable.

git clone https://github.com/LekKit/RVVM
cd RVVM
make
cd release.linux.x86_64
./rvvm_x86_64 -h

You can configure the build with USE flags. To cross-compile, pass CC=target-gcc to make. If it fails to detect features, pass ARCH/OS variables explicitly.

Examples:

make lib CC=aarch64-linux-android21-clang USE_FB=0
make lib all CC=x86_64-w64-mingw32-gcc USE_NET=1
make CFLAGS=-m32 ARCH=i386 USE_RV64=0 BUILDDIR=build BINARY=rvvm
make CC=mipseb-linux-gnu-gcc USE_JIT=0 USE_SDL=2

Alternatively, you can use CMake:

git clone https://github.com/LekKit/RVVM
cd RVVM
cmake -S. -Bbuild
cmake --build build --target all
cd build
./rvvm -h

🚀 Running

rvvm fw_payload.bin -i drive.img -m 2G -smp 2 -res 1280x720

Recommended working firmware, distro images are found in Release section

Argument explanation:

[fw_payload.bin]       Initial M-mode firmware, OpenSBI + U-Boot in this case
-k, -kernel u-boot.bin Optional S-mode kernel payload (Linux Image, U-Boot, etc)
-i, -image drive.img   Attach storage image (Raw format, NVMe as of now)
-m, -mem 2G            Memory amount (may be suffixed by k/M/G), default 256M
-s, -smp 2             Amount of cores, single-core machine by default
-res 1280x720          Changes framebuffer & VM window resolution
-rv32                  Enable 32-bit RISC-V, 64-bit by default
 . . .
-cmdline, -append ...  Override/append default kernel command line
-nogui, -nojit         Disable GUI (Use only UART), Disable JIT (for debugging)
-v                     Verbose mode

Invoke rvvm -h to see extended help.

Tested environments (Likely works elsewhere as well)

⚖️ License

This work is dual-licensed under GPL 3.0 and MPL 2.0. You can choose between one of them if you use this work.

If you wish to use this work as a component of a larger, non-GPL compliant project, you are free to do so in any form (Static linkage, binary distribution, modules) as long as you comply with the MPL 2.0 license.

For any form of software distribution, changes made precisely to this work should be made public to comply with either licenses.

Source file headers should be gradually transitioned to reflect their reusability.

🎉 Contributions

🔍 TODO

• Sparse block image format with compression/deduplication
• Suspend/resume to file, VM migration
• Linux userspace binary emulation (WIP)
• Sound (HD Audio or else)
• More RVJIT optimizations, shared caches
• FPU JIT (Complicated AF to make a conformant one)
• Vector extensions
• Other peripherals from real boards (VisionFive 2: GPIO, SPI, flash...)
• RISC-V APLIC, PCIe MSI Interrupts
• Maybe virtio devices (For better QEMU interoperability, current devices are plenty fast)
• Free page reporting via virtio-balloon
• A lot more...
• KVM hypervisor? Alternative CPU engines?

The RISC-V trade name is a registered trade mark of RISC-V International.