ncnn is a high-performance neural network inference framework optimized ...
Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC...
Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), BPF,...
Tengine is a lite, high performance, modular inference engine for embedd...
Rust version of THU uCore OS. Linux compatible.
Rocket Chip Generator
A FPGA friendly 32 bit RISC-V CPU implementation
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of bo...
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
SonicBOOM: The Berkeley Out-of-Order Machine
A debugging toolset and library for debugging embedded ARM and RISC-V ta...
oreboot is a fork of coreboot, with C removed, written in Rust.
:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V sof...
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order c...
Unix-like OS in Rust inspired by xv6-riscv