Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
To build KC705 bitstream file:
$ cd sv/prj/impl/kc705
$ make
To build and run full system unisim RTL simulation:
$ cd sv/prj/impl/asic_sim
$ make build
$ make gui
To build and run precise SystemC simulation (see github actions):
$ cmake -S ./debugger/cmake -B build
$ cd build
$ make
$ cd linuxbuild/bin
$ ./run_sysc_river_x1_gui.sh
Note: Information related to VHDL source code is obsolete and currently is updating.
This repository provides open source System-on-Chip implementation based on open source RISC-V specifications. SOC project includes general set of peripheries, FPGA CADs projects files, own implementation of the Windows/Linux debugger and several examples that help to run your firmware on almost any FPGA boards. Satellite Navigation (GPS/GLONASS/Galileo) modules were stubbed in this repository and can be requested separately.
That's a VHDL RISC-V ISA implementation used in a several projects including
the multi-sytem Satellite Navigation receiver. It is great for an
embedded applications with active usage of 64-bits computations (like DSP).
River CPU includes the following tools and features:
You can find several demonstration videos here of working with the Dual-Core SoC on FPGA and with the emulated platforms.
SoC documentation in .pdf formats.
Performance analysis is based on very compact Dhrystone v2.1. benchmark application available as the bare-metal test in $(TOP)/example/dhrystone21 folder and entirely ported into Zephyr shell (see animated gif below). Benchmark was executed with enabled (-O0) and disabled (-O2) optimization to define HW and GCC-compiler advantages. All sources are available and could be run on the simulator or on the different FPGA targets.
Target | Git tag | Dhrystone per sec, -O0, 60 MHz |
Dhrystone per sec, -O2, 60 MHz |
Information. |
---|---|---|---|---|
RISC-V simulator | latest | 76824.0 | 176469.0 | GCC 7.1.1 with the compressed instructions set. |
RISC-V simulator | latest | 77719.0 | 184074.0 | GCC 8.3.1 with the compressed instructions set. |
"River" CPU | latest | 48581 | 135432.0 | GCC 8.3.1 with the compressed instructions set. |
ARM simulator | latest | 78451.0 | 162600.0 | arm-none-eabi-gcc 7.2.0, ARM ISA only. |
Cortex-R5 ARM | No | 20561.0 | 42401.0 | arm-none-eabi-gcc 7.2.0, custom FPGA system: Single-Core, MPU enabled, Caches disabled. |
Cortex-R5 ARM | No | 54052.0 | 132446.0 | arm-none-eabi-gcc 7.2.0, custom FPGA system: Single-Core, MPU enabled, Caches enabled. |
Cortex-M3 Thumb2 | arm_vhdl | soon | soon | arm-none-eabi-gcc 7.2.0, custom FPGA system |
"LEON3" SPARC V8 | No | 48229.0 | 119515.0 | sparc-elf-gcc 4.4.2, custom FPGA system. |
Access to all memory banks and peripheries for all targets (including ARM and Leon3) is made in the same clock domain and always is one clock (without wait-states). So, this benchmark result (Dhrystone per seconds) shows performance of the CPU with integer instructions and degradation of the CPI relative ideal (simulation) case.
CPU | Clocks-Per-Instruction, CPI |
Description. |
---|---|---|
Cortext-R5 | 1.22 | This is dual-issue processor capable to execute a pair of instructions per one clock. It's a very good but quite expensive CPU. |
LEON3 | 1.5 | CPI information from here. |
River | 1.35 | Free-to-use and highly customizable CPU. I/D caches are enabled: 4-ways, 16 KB each. Reference Manual. |
Cortex-M3 | soon | RTL is under development. |
Since the tag 'v7.0' RIVER CPU is the main processor in the system and all issues related to Rocket-chip instance will be supported only by request.
This repository consists of three sub-projects each in own subfolder:
You can use the pre-built FPGA image (for Xilinx ML605 or KC705 board) and any serial console application (putty, screen or other) to run Dhrystone v2.1 benchmark as on the animated picture below.
Unpack and load file image riscv_soc.bit from /rtl/bit_files/ into FPGA board.
Connect to serial port. I used standard console utility screen on Ubuntu.
$ sudo apt-get install screen
$ sudo screen /dev/ttyUSB0 115200
Use button "Center" to reset FPGA system and reprint initial messages (or just press Enter):
To end the session, use Ctrl-A, Shift-K
How to build simulator from scratch see here
It should look like the following:
There's dependency of two others open source projects:
Default VHDL configuration enables River CPU with full debug support.