Mips Simulator Save
💻 A 5-stage pipeline MIPS CPU design in Haskell.
MIPS-Simulator
A functional MIPS CPU simulator implemented in Haskell.
A year ago, I implemented a RISC-V simulator in C++. I had long dreamed of using a functional programming language to express the circuit of a CPU. But at that time, implementing lazy-evalution in C++ is slow and painful. So the semester in Computer Architecture course, I made this MIPS simulator.
As functional programming language works well in expressing this hardware circuit logic, I'm implementing A MIPS CPU, just by directly translating Haskell into Verilog.
All CPU and CPU simulators I've made are listed below.
| Technique | Implementation | |
|---|---|---|
| RISC-V v1 | 5-stage pipeline simulator | C++ |
| RISC-V v2 | dynamic scheduling simulator Tomasulo + Speculation |
C++ |
| MIPS | 5-stage pipeline simulator | Haskell |
| MIPS | 5-stage pipeline CPU | Verilog |
Usage
Currently I haven't implemented a command-line interface for interacting with this simulator. You can only run tests or hack it yourself for now.
Install Stack and simply run:
stack test
Roadmap
- Single-Cycle Processor
- R type
- I type
- ALU test
- Compare and shift
- Support HI and LO, multiply and division
- Branch instruction
- jump and link
- J type
- Memory operations
- unsigned / high addr memory operations
- Multi-Cycle Processor
- Data path
- Stalling
- Forwarding
- Branch Prediction
- Advanced Branch Predictor
- Hazard Tests
Reference
- https://uweb.engr.arizona.edu/~ece369/Resources/spim/MIPSReference.pdf (some opcode is wrong in this pdf)
- http://www.mrc.uidaho.edu/mrc/people/jff/digital/MIPSir.html
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