Krevanth ZAP Save Abandoned
ZAP is a superpipelined ARMv5TE ISA (pre-2000s) compatible processor with cache and MMU. Copyright (C) 2016-2022 Revanth Kamaraj
Project README
ZAP : A Superpipelined ARM v5TE Processor with Caches and MMU
by Revanth Kamaraj (krevanth)
- 11 Stage Super-Pipeline that can execute most ARM instruction in 1 clock cycle.
- Binary compatible with ARMv5TE (16/32-bit support with DSP extensions, CP15 coprocessor present)
- Single Clock Fully Synchronous Posedge Flip-Flop Based Design (FPGA/ASIC Friendly)
Open Issues (2016-2022): https://github.com/krevanth/ZAP/issues
Closed Issues (2016-2022): https://github.com/krevanth/ZAP/issues?q=is%3Aissue+is%3Aclosed
Development History
| Date Range | Summary |
|---|---|
| 26 Aug 2016 | PROJECT STARTED |
| 26 Aug 2016 to 31 Dec 2016 | v4 implementation with cache and MMU. |
| 01 Jan 2017 to 31 Dec 2018 | Reorganized files. Added T extension support, some v5 support, cache and MMU. Fixed UART. |
| 01 Jan 2019 to 31 Mar 2022 | NO UPATES DURING THIS TIMEFRAME. |
| 01 Apr 2022 to 14 Apr 2022 | Reorganized files, added v5+E extension support. Improved timing. |
| 15 Apr 2022 | PROJECT DEVELOPMENT HALTED. |
Author : Revanth Kamaraj (Username: krevanth, E-Mail: [email protected]).
krevanth ~ git version 2.35.2
-----------------------------
Project: ZAP
HEAD: 14f1a9e (tmp_branch, origin/tmp_branch)
Created: 26 Aug 2016
Repo set to read only: 16 Apr 2022
Languages: ● Verilog (98.1 %) ● Perl (1.0 %) ● C (0.8 %)
Authors: Revanth Kamaraj(Username: krevanth, E-Mail:[email protected]), 458 commits
Repo: https://github.com/krevanth/ZAP.git
Commits: 458
Lines of code: 14621
Size: 1.18 MiB (95 files)
License: GPL-2.0-only
COPYRIGHT (C) 2016-2022 REVANTH KAMARAJ (KREVANTH)
THIS PROGRAM IS FREE SOFTWARE; YOU CAN REDISTRIBUTE IT AND/OR MODIFY
IT UNDER THE TERMS OF THE GNU GENERAL PUBLIC LICENSE AS PUBLISHED BY
THE FREE SOFTWARE FOUNDATION; EITHER VERSION 2 OF THE LICENSE, OR
(AT YOUR OPTION) ANY LATER VERSION.
THIS PROGRAM IS DISTRIBUTED IN THE HOPE THAT IT WILL BE USEFUL,
BUT WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED WARRANTY OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. SEE THE
GNU GENERAL PUBLIC LICENSE FOR MORE DETAILS.
YOU SHOULD HAVE RECEIVED A COPY OF THE GNU GENERAL PUBLIC LICENSE ALONG
WITH THIS PROGRAM; IF NOT, WRITE TO THE FREE SOFTWARE FOUNDATION, INC.,
51 FRANKLIN STREET, FIFTH FLOOR, BOSTON, MA 02110-1301 USA.
1. Introduction
ZAP is a Verilog processor core that can execute ARMv5TE binaries. Note that ZAP is NOT an ARM clone. ZAP is a completely different implementation and unique superpipelined microarchitecture built from scratch with the aim of providing maximum performance for typical FPGA/ASIC targets.
ZAP can run binaries compiled for legacy ARM cores (ARMv5TE ISA) and provides full software compatibility including architecturally exposed CPU modes, short instruction support, FCSE, cache, MMU, TLBs and the CP15 interface layer for cache and MMU control. The software compatibility allows ZAP to boot full operating systems like Linux.
This is one of the major projects done by me during my master's degree at university (JNTUH/VEDAIIT). In 2016, this project was presented at the 2016 ORCONF student design contest (https://www.fossi-foundation.org/2016/10/13/designcontest).
This is a fun project started by me on August 29th 2016. Majority of the developement was done by me in the 2016 to 2017 timeframe itself. Note that as of April 2022, I have completely halted development of this project and will only accept bug fixes.
2. Microarchitecture and Implementation
2.1. Superpipelined Microarchitecture
- Please note that the processor is not an ARM clone but a completely different RTL and unique microarchitecture design, microarchitected by me from scratch, in synthesizable Verilog-2001.
- Design is fully synchronous to rising edge of clock. Design is built around posedge driven flip-flops and memory blocks. Design uses a single clock.
- Reset is synchronous to the rising edge of the clock (Sync Reset).
- Deep 11-stage pipeline design to achieve high operating frequency.
- Stages: IAddressGenerator, Fetch/ICacheRead, InstrBuffer, CompressedDecode, PreDecode, Decode, Issue, Shift/Multiply, Execute/DAddressGenerator, DCacheRead, RegisterWriteback
- Pipeline has extensive bypass network that is optimized to resolve dependencies. This allows for maximum throughput.
- Pipeline has a unique dual feedback implementation to further optimize dependency resolution.
- This permits instructions that use the shifter to not stall a subsequent dependent command if the subsequent dependent command command specifies zero shift (LSL #0).
- Pipeline has a unique dual feedback implementation to further optimize dependency resolution.
- Most operations execute at a rate of 1 operation per clock.
- The deep pipeline allows the processor to reach ~100MHz on a Spartan/Artix 7-Series FPGA.
- Each multiplication/MAC operation takes 4 cycles to complete.
- The pipeline stalls when a multiply/MAC operation is in progress.
- The result is available 1 cycle after the MAC operation completes.
- Having a dependent instruction right after the multiply/MAC will incur an additional cycle of stall.
- CISC-style instructions are sequenced as simpler micro-ops for the internal RISC core.
- A direct mapped bimodal branch predictor is used to improve performance to counter the longer pipeline.
- Two write ports for the register file allow LDR/STR with writeback to execute as a single instruction.
- Register file is implemented using flip-flops.
- Cache and MMU is supported and configurable through parameters.
- Cache latency on read and write hit is 1 cycle.
- Basically, if a hit occurs, it will not insert any bubbles or stall the pipeline.
- Note that data is available for instructions a cycle after the cache read. A dependent instruction right after will stall the pipeline for an additional cycle.
- Note that a cache miss will (effectively) stall the entire pipeline.
- Uses direct mapped split caches (VIVT) and direct mapped TLBs. Individual TLBs RAMs are provided for 1M/64K/4K/1K pages, whose size can be configured through Verilog paramters.
- Provides Verilog parameters for configuration including cache and TLB parameters.
- Design is microarchitected and implemented in synthesizable Verilog-2001 HDL.
2.1.1. Clock and Reset
2.1.1.1. Clock
- The processor uses a synchronous single clock based design style.
- All sequential elements are edge sensitive and are driven on the rising edge of clock.
- All IO interfaces are also driven on the rising edge of the clock.
2.1.1.2. Reset
- Reset should be:
- Synchronous to the rising edge of clock.
- Should be pulsed high for atleast 1 cycle of clock.
- Active high and should be asserted and deasserted on the rising edge of clock.
- One cycle after reset deassertion:
- Processor will start executing instructions from physical bus address 0x0.
- Processor will be in supervisory mode (SVC).
3. Coprocessor 15 CSRs
Please refer to the arch spec for CP15 CSR requirements.
- Register 1: Cache and MMU control.
- Register 2: Translation Base.
- Register 3: Domain Access Control.
- Register 5: FSR.
- Register 6: FAR.
- Register 8: TLB functions.
- Register 7: Cache functions.
- The arch spec allows for a subset of the functions to be implemented for register 7.
- These are supported (Read as {opcode2, crm}) in ZAP for register 7:
- CASE_FLUSH_ID_CACHE = 7'b000_0111
- CASE_FLUSH_I_CACHE = 7'b000_0101
- CASE_FLUSH_D_CACHE = 7'b000_0110
- CASE_CLEAN_ID_CACHE = 7'b000_1011
- CASE_CLEAN_D_CACHE = 7'b000_1010
- CASE_CLEAN_AND_FLUSH_ID_CACHE = 7'b000_1111
- CASE_CLEAN_AND_FLUSH_D_CACHE = 7'b000_1110
- Register 13: FCSE Register.
3. Usage
- To use the ZAP processor in your project:
- Add all the files *.v in src/rtl/ to your project.
- Add src/rtl/ to your tools search path to allow it to pick up Verilog headers.
- Instantiate the top level CPU module, zap_top, in your SOC.
- The processor provides a Wishbone B3 bus. It is recommended that you use it in registered feedback cycle mode.
- Interrupts should be routed from the appropriate VIC. Interrupts are level sensitive and should be synchronous to the CPU clock.
- Wire up clock and reset as required.
3.1. Installation (GIT)
To get the files of the ZAP processor, please execute:
git clone https://github.com/krevanth/ZAP.git
3.2. CPU Configuration (Verilog Parameters)
| Parameter | Default | Description |
|---|---|---|
| BP_ENTRIES | 1024 | Branch Predictor Settings. Predictor RAM depth. Must be 2^n and > 2 |
| FIFO_DEPTH | 4 | Command FIFO depth. Must be 2^n and > 2 |
| STORE_BUFFER_DEPTH | 16 | Depth of the store buffer. Must be 2^n and > 2 |
| DATA_SECTION_TLB_ENTRIES | 4 | Data Cache/MMU Configuration. Section TLB entries. Must be 2^n (n > 0) |
| DATA_LPAGE_TLB_ENTRIES | 8 | Data Cache/MMU Configuration. Large page TLB entries. Must be 2^n (n > 0) |
| DATA_SPAGE_TLB_ENTRIES | 16 | Data Cache/MMU Configuration. Small page TLB entries. Must be 2^n (n > 0) |
| DATA_FPAGE_TLB_ENTRIES | 32 | Data Cache/MMU Configuration. Tiny page TLB entries. Must be 2^n (n > 0) |
| DATA_CACHE_SIZE | 4096 | Data Cache/MMU Configuration. Cache size in bytes. Must be at least 256B and 2^n |
| CODE_SECTION_TLB_ENTRIES | 4 | Instruction Cache/MMU Configuration. Section TLB entries. Must be 2^n (n > 0) |
| CODE_LPAGE_TLB_ENTRIES | 8 | Instruction Cache/MMU Configuration. Large page TLB entries. Must be 2^n (n > 0) |
| CODE_SPAGE_TLB_ENTRIES | 16 | Instruction Cache/MMU Configuration. Small page TLB entries. Must be 2^n (n > 0) |
| CODE_FPAGE_TLB_ENTRIES | 32 | Instruction Cache/MMU Configuration. Tiny page TLB entries. Must be 2^n (n > 0) |
| CODE_CACHE_SIZE | 4096 | Instruction Cache/MMU Configuration. Cache size in bytes. Must be at least 256B and 2^n |
| DATA_CACHE_LINE | 64 | Cache Line for Data (Bytes). Keep 2^n and >= 16 Bytes |
| CODE_CACHE_LINE | 64 | Cache Line for Code (Bytes). Keep 2^n and >= 16 Bytes |
3.3. CPU Top Level IO Interface (src/rtl/zap_top.v, Module: zap_top)
32-Bit Pipelined Wishbone B3 Compatible Bus (CTI/BTE Enabled)
| Dir | Size | Port | Description | Synchronous to |
|---|---|---|---|---|
| input | 1 | i_clk | Clock. All logic is clocked on the rising edge of this signal. | -- |
| input | 1 | i_reset | Reset. Synchronous active high reset. | Rising edge of i_clk |
| input | 1 | i_irq | Interrupt. Level Sensitive. | Rising edge of i_clk |
| input | 1 | i_fiq | Fast Interrupt. Level Sensitive. | Rising edge of i_clk |
| output | 1 | o_wb_cyc | Wishbone CYC signal. | Rising edge of i_clk |
| output | 1 | o_wb_stb | WIshbone STB signal. | Rising edge of i_clk |
| output | [31:0] | o_wb_adr | Wishbone address signal. | Rising edge of i_clk |
| output | 1 | o_wb_we | Wishbone write enable signal. | Rising edge of i_clk |
| output | [31:0] | o_wb_dat | Wishbone data output signal. | Rising edge of i_clk |
| output | [3:0] | o_wb_sel | Wishbone byte select signal. | Rising edge of i_clk |
| output | [2:0] | o_wb_cti | Wishbone Cycle Type Indicator (Supported modes: Incrementing Burst, End of Burst) | Rising edge of i_clk |
| output | [1:0] | o_wb_bte | Wishbone Burst Type Indicator (Supported modes: Linear) | Rising edge of i_clk |
| input | 1 | i_wb_ack | Wishbone ack signal. Recommended to use Wishbone registered feedback cycles. | Rising edge of i_clk |
| input | [31:0] | i_wb_dat | Wishbone data input signal. | Rising edge of i_clk |
3.4. Run Sample Tests (Demo)
- Let the variable $test_name hold the name of the test.
- See the src/ts directory for some basic tests pre-installed.
- Available test names include: factorial (tests cache, MMU, interrupts), arm_test (Modified test suite that is derived from the ARM4U project), thumb_test (Very basic test), uart (Echo test).
- New tests can be added using these as starting templates.
- Please note that these will be run on the sample TB SOC platform (chip_top) that consist of the ZAP processor, 2 x UARTs, a VIC and a timer.
- Tests will produce appropriate logs and wave files in the obj/src/ts/$test_name folder.
For debian based distros:
sudo apt-get install gcc-arm-none-eabi binutils-arm-none-eabi gdb openocd iverilog gtkwave make perl xterm gcc # Install all required packages on the system.
cd $PROJ_ROOT/src/ts/$test_name # $PROJ_ROOT is the project directory.
make # Runs the test using IVerilog.
cd $PROJ_ROOT/obj/ts/$test_name # Switch to object folder.
gvim zap.log.gz # View the log file
gtkwave zap.vcd.gz # Exists if selected by Config.cfg of that test case.
For arch based distros:
sudo pacman -S arm-none-eabi-gcc arm-none-eabi-binutils gdb openocd iverilog gtkwave make perl xterm gcc # Install all required packages on the system.
cd $PROJ_ROOT/src/ts/$test_name # $PROJ_ROOT is the project directory.
make # Runs the test using IVerilog.
cd $PROJ_ROOT/obj/ts/$test_name # Switch to object folder.
gvim zap.log.gz # View the log file
gtkwave zap.vcd.gz # Exists if selected by Config.cfg of that test case.
4. FPGA Device Utilization on 7a35t-ftg256-2L (Default Parameters)
Slice Logic
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|---|---|---|---|---|---|
| Slice LUTs | 16105 | 0 | 0 | 20800 | 77.43 |
| LUT as Logic | 14291 | 0 | 0 | 20800 | 68.71 |
| LUT as Memory | 1814 | 0 | 0 | 9600 | 18.90 |
| LUT as Distributed RAM | 1814 | 0 | |||
| LUT as Shift Register | 0 | 0 | |||
| Slice Registers | 9134 | 0 | 0 | 41600 | 21.96 |
| Register as Flip Flop | 9134 | 0 | 0 | 41600 | 21.96 |
| Register as Latch | 0 | 0 | 0 | 41600 | 0.00 |
| F7 Muxes | 787 | 0 | 0 | 16300 | 4.83 |
| F8 Muxes | 261 | 0 | 0 | 8150 | 3.20 |
Summary of Registers by Type
| Total | Clock Enable | Synchronous | Asynchronous |
|---|---|---|---|
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 27 | Yes | Set | - |
| 9107 | Yes | Reset | - |
Memory
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|---|---|---|---|---|---|
| Block RAM Tile | 4.5 | 0 | 0 | 50 | 9.00 |
| RAMB36/FIFO* | 4 | 0 | 0 | 50 | 8.00 |
| RAMB36E1 only | 4 | ||||
| RAMB18 | 1 | 0 | 0 | 100 | 1.00 |
| RAMB18E1 only | 1 |
- Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
DSP
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|---|---|---|---|---|---|
| DSPs | 4 | 0 | 0 | 90 | 4.44 |
| DSP48E1 only | 4 |
Primitives
| Ref Name | Used | Functional Category |
|---|---|---|
| FDRE | 9107 | Flop |
| FDSE | 27 | Flop |
| LUT6 | 8610 | LUT |
| LUT5 | 2408 | LUT |
| LUT3 | 2352 | LUT |
| LUT4 | 1885 | LUT |
| RAMD64E | 1536 | Distributed Memory |
| MUXF7 | 787 | MuxFx |
| LUT2 | 678 | LUT |
| RAMD32 | 416 | Distributed Memory |
| MUXF8 | 261 | MuxFx |
| CARRY4 | 207 | CarryLogic |
| RAMS32 | 138 | Distributed Memory |
| LUT1 | 97 | LUT |
| RAMB36E1 | 4 | Block Memory |
| DSP48E1 | 4 | Block Arithmetic |
| RAMB18E1 | 1 | Block Memory |
RAM Mapping Report
Block RAM: Final Mapping Report
When porting to ASIC, these block RAMs should be replaced with equivalent dual port ASIC memories.
| Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
|---|---|---|---|---|---|---|---|---|---|---|
| zap_cache:/u_zap_cache_tag_ram | u_zap_ram_simple_tag/mem_reg | 64 x 46(READ_FIRST) | W | 64 x 46(WRITE_FIRST) | R | Port A and B | 0 | 1 | ||
| zap_cache:/u_zap_cache_tag_ram | u_zap_ram_simple_tag/mem_reg | 64 x 46(READ_FIRST) | W | 64 x 46(WRITE_FIRST) | R | Port A and B | 0 | 1 | ||
| u_zap_corei_2/u_zap_fetch_main | u_br_ram/mem_reg | 1 K x 2(READ_FIRST) | W | 1 K x 2(WRITE_FIRST) | R | Port A and B | 1 | 0 |
Distributed RAM: Final Mapping Report
####### Data Cache 64 Byte Wide Memory
When porting to ASIC, these block RAMs should be replaced with equivalent dual port ASIC memories. ASIC should combine genblk1[*].u_zap_ram_simple_data_ram byte wide RAMs into a wider memory with byte enables. There should be a tradeoff between memory width and area.
| Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
|---|---|---|---|---|
| zap_cache:/u_zap_cache_tag_ram | genblk1[0].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[1].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[2].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[3].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[4].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[5].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[6].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[7].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[8].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[9].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[10].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[11].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[12].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[13].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[14].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[15].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[16].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[17].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[18].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[19].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[20].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[21].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[22].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[23].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[24].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[25].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[26].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[27].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[28].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[29].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[30].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[31].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[32].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[33].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[34].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[35].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[36].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[37].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[38].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[39].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[40].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[41].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[42].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[43].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[44].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[45].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[46].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[47].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[48].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[49].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[50].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[51].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[52].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[53].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[54].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[55].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[56].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[57].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[58].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[59].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[60].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[61].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[62].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[63].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
####### Code Cache 64 Byte Wide Memory
When porting to ASIC, these block RAMs should be replaced with equivalent dual port ASIC memories. ASIC should combine genblk1[*].u_zap_ram_simple_data_ram byte wide RAMs into a wider memory with byte enables. There should be a tradeoff between memory width and area.
| Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
|---|---|---|---|---|
| zap_cache:/u_zap_cache_tag_ram | genblk1[0].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[1].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[2].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[3].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[4].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[5].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[6].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[7].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[8].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[9].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[10].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[11].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[12].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[13].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[14].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[15].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[16].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[17].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[18].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[19].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[20].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[21].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[22].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[23].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[24].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[25].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[26].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[27].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[28].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[29].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[30].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[31].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[32].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[33].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[34].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[35].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[36].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[37].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[38].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[39].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[40].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[41].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[42].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[43].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[44].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[45].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[46].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[47].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[48].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[49].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[50].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[51].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[52].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[53].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[54].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[55].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[56].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[57].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[58].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[59].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[60].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[61].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[62].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
| zap_cache:/u_zap_cache_tag_ram | genblk1[63].u_zap_ram_simple_data_ram/mem_reg | Implied | 64 x 8 | RAM64M x 3 |
####### Data TLB RAMs
When porting to ASIC, these block RAMs should be replaced with equivalent dual port ASIC memories.
| Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
|---|---|---|---|---|
| zap_cache:/u_zap_tlb | u_section_tlb/u_ram_simple/mem_reg | Implied | 4 x 42 | RAM32M x 7 |
| zap_cache:/u_zap_tlb | u_lpage_tlb/u_ram_simple/mem_reg | Implied | 8 x 45 | RAM32M x 8 |
| zap_cache:/u_zap_tlb | u_spage_tlb/u_ram_simple/mem_reg | Implied | 16 x 52 | RAM32M x 9 |
####### Code TLB RAMs
When porting to ASIC, these block RAMs should be replaced with equivalent dual port ASIC memories.
| Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
|---|---|---|---|---|
| zap_cache:/u_zap_tlb | u_section_tlb/u_ram_simple/mem_reg | Implied | 4 x 42 | RAM32M x 7 |
| zap_cache:/u_zap_tlb | u_lpage_tlb/u_ram_simple/mem_reg | Implied | 8 x 45 | RAM32M x 8 |
| zap_cache:/u_zap_tlb | u_spage_tlb/u_ram_simple/mem_reg | Implied | 16 x 52 | RAM32M x 9 |
####### FIFO RAMs
When porting to ASIC, these block RAMs should be replaced with equivalent dual port ASIC memories.
| Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
|---|---|---|---|---|
| zap_top | u_zap_wb_adapter/U_STORE_FIFO/mem_reg | Implied | 16 x 70 | RAM32M x 12 |
| u_zap_corei_2/U_ZAP_FIFO | USF/mem_reg | Implied | 4 x 67 | RAM32M x 12 |
5. Design Quality Checks
checking no_clock (0)
There are 0 register/latch pins with no clock.
checking constant_clock (0)
There are 0 register/latch pins with constant_clock.
checking pulse_width_clock (0)
There are 0 register/latch pins which need pulse_width check
checking unconstrained_internal_endpoints (0)
There are 0 pins that are not constrained for maximum delay.
There are 0 pins that are not constrained for maximum delay due to constant clock.
checking no_input_delay (0)
There are 0 input ports with no input delay specified.
There are 0 input ports with no input delay but user has a false path constraint.
checking no_output_delay (0)
There are 0 ports with no output delay specified.
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
checking multiple_clock (0)
There are 0 register/latch pins with multiple clocks.
checking generated_clocks (0)
There are 0 generated clocks that are not connected to a clock source.
checking loops (0)
There are 0 combinational loops in the design.
checking partial_input_delay (0)
There are 0 input ports with partial input delay specified.
checking partial_output_delay (0)
There are 0 ports with partial output delay specified.
checking latch_loops (0)
There are 0 combinational latch loops in the design through latch input
6. Timing Report on 7a35t-ftg256-2L (Default Parameters)
| Clock | Waveform(ns) | Period(ns) | Frequency(MHz) | WNS(ns) | TNS(ns) | TNS Failing Endpoints | TNS Total Endpoints | WHS(ns) | THS(ns) | THS Failing Endpoints | THS Total Endpoints | WPWS(ns) | TPWS(ns) | TPWS Failing Endpoints | TPWS Total Endpoints |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| i_clk | {0.000 4.546} | 9.091 | 109.999 | -0.885 | -759.965 | 2614 | 35514 | 0.077 | 0.000 | 0 | 35514 | 3.415 | 0.000 | 0 | 11377 |
7. References
- COMPUTER ARCHITECTURE: A QUANTITATIVE APPROACH 5TH EDITION JOHN L. HENNESSY, DAVID A. PATTERSON (ISBN: 9788178672663)
- ARM SYSTEM-ON-CHIP ARCHITECTURE BY STEVE FURBER (ISBN: 9788131708408)
- VERILOG HDL: A GUIDE TO DIGITAL DESIGN AND SYNTHESIS BY SAMIR PALNITKAR (ISBN: 9788177589184)
Open Source Agenda is not affiliated with "Krevanth ZAP" Project. README Source: krevanth/ZAP
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