sliding DFT for FPGA, targetting Lattice ICE40 1k
having a go at some DSP on an FPGA. I'm basing the design on this paper:
http://www.comm.toronto.edu/~dimitris/ece431/slidingdft.pdf
This is a sliding discrete Fourier transform. It requires two real adds and one complex multiply per frequency bin. The transform is run for every new sample taken.
Using an 8k device:
IOs 18 / 206
GBs 0 / 8
GB_IOs 0 / 8
LCs 3619 / 7680
DFF 120
CARRY 512
CARRY, DFF 39
DFF PASS 86
CARRY PASS 165
BRAMs 13 / 32
WARMBOOTs 0 / 1
PLLs 1 / 2