Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe
The goal of this project is to provide a PCIe interface in Amaranth HDL.
There already exists a PCIe physical layer by whitequark called Yumewatari and a TLP and DMA layer by enjoy-digital called litepcie written in omigen.
Execute python setup.py develop
in the Gateware folder
python test_pcie_virtual.py
in the Tests folder to run the simulationgtkwave test.gtkw
to view the resultsSee the Setup page in the Wiki
pci init
in u-boot)python test_pcie_phy.py run
in the Tests folder to upload the gateware to the ECP5python test_pcie_phy.py grab
to get DLLPs received in the L0 state (and the time since it has been in the L0 state).
Sometimes the last few results are invalid and the program doesn't halt, end it by pressing Ctrl + C
.
It should show something like this:Data is composed of the first symbol received in one clock cycle, its representation in hexadecimal, the same for the second symbol. The time is in clock cycles since entering L0, which are 8 ns each.