awesome-riscv

A curated list of awesome RISC-V implementations

Open Source implementations

Repository	Language	arch	microarch	Target	License	:star:
cva6	SystemVerilog	rv64gc	6 stage	FPGA,ASIC	Solderpad
CV32E40P	SystemVerilog	rv32imcf	4 stage	FPGA,ASIC	Solderpad
FWRISC-S	SystemVerilog	rv32i[mc]		FPGA	Apache2
Ibex	SystemVerilog	rv32imc	2 stage	ASIC	Apache2
Minerva	Python,nMigen	rv32im	6 stage	FPGA	BSD
PicoRV32	Verilog	rv32{i,e}[m][c]	?	FPGA,ASIC	ISC
riscv-mini	Scala,Chisel	rv32i	3 stage	ASIC	BSD
Rocket	Scala,Chisel	rv32ima	5? stage	ASIC	BSD
SERV	Verilog	rv32	0-calories	FPGA	ISC
SweRV	SystemVerilog	rv32imc	9-stage, dual-issue, superscalar	ASIC	Apache2
VexRiscv	Scala,SpinalHDL	rv32i[m][c][a]	2-5 stage	FPGA	MIT
wyvernSemi	Verilog	rv32imafdc	5 stage	FPGA	GPL3
NEORV32	VHDL	rv32[i/e][a][c][m][u]x[Zbb]...	2 stage	FPGA	BSD3
vroom	Verilog	rv64imafdchb[v]	OOO, 7+ stage, SMT-2	ASIC	GPL3
NaxRiscv	Scala,SpinalHDL	rv32/64imasu	OOO, superscalar, register renaming	FPGA	MIT

License

To the extent possible under law, Aliaksei Chapyzhenka has waived all copyright and related or neighboring rights to this work.