A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000...
A Python package to use FPGA development tools programmatically.
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast F...
Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC seri...
FPGA accelerated TinyYOLO v2 object detection neural network
16-bit Adder Multiplier hardware on Digilent Basys 3
Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
Virtio implementation in SystemVerilog
⚙Hardware Synthesis Laboratory Using Verilog
Project for an RPU RISC-V system on chip implementation on the Digilent ...
Xilinx PCIe to MIG DDR4 example designs and custom part data files
Objective of this project was to emulate a Basketball scoreboard, with t...