Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
This project contains fully pipelined integer unscaled and scaled (truncated LSB) FFT/IFFT cores for FPGA, Scheme: Radix-2, Decimation in frequency and decimation in time;
Integer data type and twiddles with configurable data width.
Code language - VHDL, Verilog
Vendor: Xilinx, 6/7-series, Ultrascale, Ultrascale+;
Smallest FPGA resourses and highest processing frequency that you ever seen!
License: GNU GPL 3.0.
Title | Universal integer FFT cores (Xilinx FPGAs) |
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Author | Alexander Kapitanov |
Project | Habrahabr |
Project lang | VHDL, Verilog |
Vendor | Xilinx: 6/7-series, Ultrascale, US+ |
Release Date | 13 May 2018 |
Last Update | 11 Jan 2019 |
"half" means that you should set output flow: Re or Im part.
Multipliers:
Adder:
Delay line:
Twiddles:
Buffers:
inbuf_half_path – simple input buffer, perform flow into two flows: [0 .. NFFT/2), (NFFT/2 .. NFFT-1], single clock,
outbuf_half_path – simple input buffer, merge two flows into one signal, single clock,
iobuf_flow_int2 – Mode-1: BITREV = FALSE: convert Interleave-2 flow into two parts of input flows, Mode-2: BITREV = TRUE: convert two-half flows into Interleave-2 signal.
int_bitrev_ord – simple converter data from bit-reverse to natural order.