SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Pro...
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus...
AMBA AXI VIP
SystemVerilog linter
Code generation tool for control and status registers
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python ...
Test suite designed to check compliance with the SystemVerilog standard.
CMake, SystemVerilog and SystemC utilities for creating, building and te...
FPGA-based USB fast data transmission using FT232H/FT600 chip. 使用FT232...
An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted...
Repurposing existing HDL tools to help writing better code
Tool to generate register RTL, models, and docs using SystemRDL or JSpec...
Universal Hardware Data Model. A complete modeling of the IEEE SystemVer...
An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless...
This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.