SCR1 is a high-quality open-source RISC-V MCU core in Verilog
VeeR EH1 core
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
A 32-bit RISC-V emulator in a shader (and C)
:stars: List of software (HW interfaces, libs, protocols, etc) specifica...
RISC-V processor emulator written in Rust+WASM
RISC-V Cores, SoC platforms and SoCs
The Eclipse Embedded CDT plug-ins for Arm & RISC-V C/C++ developers (for...
PLCT Lab ❤️ Interns!
RISC-V Guide. Learn all about the RISC-V computer architecture along wit...
JTAG probe firmware
C++20 RISC-V RV32/64/128 userspace emulator library
Self-hosting metacompiled Forth, bootstrapping from a few lines of C; ta...
RISC-V Assembler and Runtime Simulator
The RISC-V software tools list, as seen on riscv.org