OpenLane is an automated RTL to GDSII flow based on several components i...
VeeR EH1 core
QKeras: a quantization deep learning library for Tensorflow Keras
VeeR EL2 Core
A dual clock asynchronous FIFO written in verilog, tested with Icarus Ve...
🎲 A Tiny and Platform-Independent True Random Number Generator for any ...
Open Application-Specific Instruction Set processor tools (OpenASIP)
Standard Cell Library based Memory Compiler using FF/Latch cells
An AXI4 crossbar implementation in SystemVerilog
Quasar 2.0: Chisel equivalent of SweRV-EL2