Open source Zynq timestamping implementation from Software Radio Systems (SRS)
This repository contains the source code of a timestamping mechanism developed by SRS for both Zynq MPSoC and RFSoC devices, including RTL and C code, project generation scripts and extensive documentation. The solution is targeting a typical SDR implementation in which the transmission and reception of I/Q samples is triggered by a call to a software function. Two different approaches are supported towards this end:
For the sake of convenience this repository includes the code which is specific to the Zynq timestamping solution and uses submodules for the related code that is external to it, including the srsRAN 4G/5G software radio suite and Analog Devices HDL library. The latter is used because the timestamping solution is targeting AD936x-based front-ends for MPSoC architectures.
The full details of the Zynq timestamping solution can be found in the documentation page. Additionally, dedicated application notes are covering all required steps from build to test:
We recommend you to go through the application notes, as the detailed steps can be (often easily) modified/reused to target different boards and/or SDR applications.
Please, use the Zynq timestamping Discussions space for discussion and community support. Make sure to read the overview and to follow the guidelines when opening a new discussion point.
The solution has been developed, validated and tested using:
Vivado 2019.2
SRS Python Tools:
cd python_tools
sudo pip3 install -U pip
pip3 install .
[optional] For documentation:
npm install teroshdl
To clone the repository and the utilized submodules:
git clone --recursive
Pre-built images for all supported boards can be found attached as an asset to the released code.