Verilog to Routing -- Open Source CAD Flow for FPGA Research
Code version used to create FCCM 2023 paper on "Placement Optimization for NoC-Enhanced FPGAs" by Srivatsan Srinivasan, Andrew Boutros and Sara Mahmoudi. Creating a release so there is a versioned artifact. This release includes the VTR code, the synthetic NoC benchmarks, the mlp NoC benchmark, and various scripts and READMEs.
.route
filevpr --analysis
)vtr_flow/scripts/upgrade_arch.py
)vpr -h
)vpr --analsysis
is specified--route
) while short single-letter arguments are prefixed by a single dash (e.g. -h
).route
filevpr --analysis
)vtr_flow/scripts/upgrade_arch.py
)vpr -h
)vpr --analsysis
is specified--route
) while short single-letter arguments are prefixed by a single dash (e.g. -h
)