IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
PoC v1.1.2 with workarounds required for Xilinx Vivado (at least up to Vivado 2016.2).
This minor update adds constraint files for the Xilinx Artix-7 FPGA AC701 Evaluation Kit.
PoC v1.1.1 with workarounds required for Xilinx Vivado (at least up to Vivado 2016.2).
This release contains:
Finalized milestone 1.1.
Minor fixes for the first major release including the new Python infrastructure.
First major release of PoC including the new Python infrastructure.