VLSI EDA PoC Versions Save

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

v1.1.2-Vivado

7 years ago

PoC v1.1.2 with workarounds required for Xilinx Vivado (at least up to Vivado 2016.2).

v1.1.2

7 years ago

This minor update adds constraint files for the Xilinx Artix-7 FPGA AC701 Evaluation Kit.

v1.1.1-Vivado

7 years ago

PoC v1.1.1 with workarounds required for Xilinx Vivado (at least up to Vivado 2016.2).

v1.1.1

7 years ago

This release contains:

  • A bigger and improved documentation including command line tools and the Python infrastructure
  • ModelSim support
  • UVVM integration
  • Continuous Integration on AppVeyor
  • Improved cache IP cores and better ocram simulation models
  • Improved testbenches: e.g. sorting networks tested with OSVVMs scoreboard.

v1.1.0

7 years ago

Finalized milestone 1.1.

v1.0.1

7 years ago

Minor fixes for the first major release including the new Python infrastructure.

v1.0.0

7 years ago

First major release of PoC including the new Python infrastructure.