Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
This is the last version before a major change in cont_assign and process elaboration. Up to this version, cont_assign and processes where not present in the Elaborated tree unless -elabuhdm flag was set. Post this release, they are going to be present.