Develop an end-to-end hypothetical reference model, network architectures, performance objectives and the methods to distribute, operate, monitor time synchronization within data center and much more...
Updated all NTL Closed source IP Cores to latest version including updated documentation.
Main changes: -Clock with Fractional Support -Small bugfix with Beidou as time source in the TOD Slave -other different small improvements and adaptations
Updated all NTL Closed source IP Cores to latest version including updated documentation. Added new UCM version which supports the new features in case you have an UART/USB connection to the Time Card
Main changes: -Clock with Fractional Support -Small bugfix with Beidou as time source in the TOD Slave -other different small improvements and adaptations
Updated all NTL Closed source IP Cores to latest version
Main changes: -Added GNSS Status information to the TOD Slave (for details please check the register set) -Added TSIPv1 messages support to the TOD Slave (for details please check the register set)
Other changes: -Setup of the Conf Master for the startup configuration via txt file (no functional impact) -Setup of the Conf Slave for the configuration with UCM via txt file (no functional impact)
Updated all NTL Closed source IP Cores to latest version including updated documentation. Added new UCM version which supports the new features in case you have an UART/USB connection to the Time Card
Main changes: -Added GNSS Status information to the TOD Slave (for details please check the register set) -Added TSIPv1 messages support to the TOD Slave (for details please check the register set)
Other changes: -Setup of the Conf Master for the startup configuration via txt file (no functional impact) -Setup of the Conf Slave for the configuration with UCM via txt file (no functional impact)
Added SMA input status supervision via AXI GPIO SMA STATUS (Base: 0x0014_2000) Prepared for I2C communication towards clock which can be selected via AXI GPIO EXT (Bit 31) Added Binary File with special header for field upgrade
Added BNO Reset of 100 us after FPGA is ready. Added TimeCardProduction_Celestica.bin with additional header information
Changed PCIe VID to 0x18d4 and DID to 0x1008
Swapped SMA1 <-> SMA3 and SMA2 <-> SMA4 (including LEDs).
The MsiIrq generator supports now level interrupts and handles them correctly. Enabled e.g. for AXI UART 16550.
The MsiIrq generator supports now level interrupts and handles them correctly. Enabled e.g. for AXI UART 16550.