SystemVerilog to Verilog conversion
-y
/--libdir
for specifying library directories from which to automatically load modules and interfaces used in the design that are not found in the provided input files--top
for pruning unneeded modules during conversion--write path/to/dir/
for creating an output .v
in the specified preexisting directory for each module in the converted resultstring
data type is now dropped from parameters and localparamssequence
and property
declarations.a()
)always_comb
, always_latch
, and always_ff
unconverted when tagged with an attribute/*/
is no longer interpreted as a self-closing block comment, e.g., $display("a"/*/,"b"/* */);
previously printed "ab", but now prints "a"begin
/end
when disambiguating procedural branches tagged with an attributebegin_keywords
version specifiersifdef
with no endif
--write adjacent
no longer forbids overwriting existing generated filesx = ++y;
)'1
, 'x
) via --exclude UnbasedUniszed
enum { X[3:5] }
)@(x ^ y)
)edge
eventassign
/deassign
and force
/release
)do
while
loopsfor
loop elaboration+ 0
and * 1
reg
of data sensed in an edge-controlled procedural assignmentalways_comb
and always_latch
now generate explicit sensitivity lists where necessary because of calls to functions which reference non-local datastruct
fields being converted to unsigned expressions when accessed directly<pkg>_<name>
being shadowed by elaborated packages'h1_ffff_ffff
, 4294967296
) are now truncated and produce a warning, rather than being silently extended
--oversized-numbers
parameter
or localparam
marker1'b11
, 3'sd8
, 2'o7
) are now truncated and produce a warning, rather than yielding a cryptic error1'b01
, 'h0_FFFF_FFFF
) now produce a warning@(*)