Inter-CPU asynchronous communication between Cortex-M7 and Cortex-M4 cores on STM32H7 dual core devices
Example project for inter-processor communication between 2 cores, ARM Cortex-M7 and ARM-Cortex-M4 cores.
This example demonstrates how to implement communication between both cores to exchange data.
It uses shared RAM and 2
separate ring buffers, acting like pipe (single input, single output)
in both direction. First buffer from CPU1 to CPU2, second buffer from CPU2 to CPU1.
SRAM4 is used as shared RAM in D3 domain. This RAM is preferred and suggested to be used for shared RAM in dual-core STM32H7xx series for inter-CPU communication. It is outside both domains of both CPU cores, not affecting to low-power features of each domain.
Example runs on official ST Nucleo boards for dual-core STM32H7 series, listed below.
STM32H7 dual-core CPU must have some option bytes configured to run the example properly. Example is configured for this configuration:
0x08000000
and its size is 1MB
0x08100000
and its size is 1MB
Option bytes can be configured using STM32CubeProgrammer software
Run examples with STM32CubeIDE v1.3.0 or later toolchain.