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Spi Fpga Versions
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SPI master and SPI slave for FPGA written in VHDL
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v1.1
3 years ago
Changed license to The MIT License.
Added better simulations and enabled GitHub CI.
Added Spirit Level example design for CYC1000 board.
Added sync FFs to SPI slave for elimination metastability.
Added WORD_SIZE generic.
Many minor changes, fixes and optimizations.
v1.0
6 years ago
Release v1.0:
added new version of master module with many optimalizations
added DIN_LAST input to master module, for signal control CS_N
added simulation tcl script for ModelSim
updated simulation testbench
updated example design
optimized and cleaned slave module
v0.8
6 years ago
Beta 2 release:
added SPI slave controller
added example design for EP4CE6 Starter Board
updated simulation testbench file
v0.5
7 years ago
Beta release:
first implementation of SPI master controller
not tested in hardware, only simulated
no SPI slave controller
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