Riscv Boom Versions Save

This marks the initial release of SonicBOOM (or BOOM v3.0.0). SonicBOOM 3.0.0 can achieve 6.2 CoreMark/MHz..

This is a concurrent release with Chipyard 1.3.

As this is a major BOOM release and update, this release note will summarize both changes since BOOMv2.2.3 (the last versioned release) and BOOMv2.0.0 (the last major release).

Changes since BOOMv2.2.3:

• Cache performance counters (#463)
• TAGE-based branch predictor (#456)
• Support for L0/L1 BTBs (#456)
• Repaired Return-address-stack (#456)
• Superscalar branch resolution (#456)
• Short-forwards-branch internal recoding (#456)
• Automated performance regressions with FireSim (#409)
• Bump to Chipyard 1.3 (#464)
• Fix LSU release search for memory consistency (#448)
• Improve quality of generated Verilog (#449)
• Fix bug with RoCC interface (#437)

Major Changes since BOOMv2.0.0:

• New L1 Cache and LSU with dual-issue loads
• Support for RoCC accelerators
• Refactored issue/rename stages
• Support RVC-extension
• Support PMP registers
• Support breakpoints

This marks BOOM version 2.2.3.

This is a concurrent release with Chipyard 1.1 (see github.com/ucb-bar/chipyard). Major changes include, bumping to newer Rocket Chip, improved DCache, and various bug-fixes for Linux + Fedora boot.

Changes:

• Connect clock + reset to trace port (#433 )
• Cleanup poison bit propagation (#395)
• Bump to Rocket Chip Aug. 19th version (#425 #422 #423 )
• Integrate Dromajo (#415 #421)
• AMOs generate correct exceptions (#418)
• Aggressively stall core when exception is pending (#399)
• Fix bug with badvaddr sign extension (#413)
• Clean-up core and Chipyard integration (#397 #396 #389 #392 #393 #394 #384 #385 #379 #375)
• Test Hwacha in CI (#338 )
• Bump CI docker image (#404 #402)
• Cleanup documentation (#400 #368 #367)
• Misc. RoCC fixes (#401)
• Always enable fast wakeups (#391)
• Disable Unified Issue Queues (#387)
• New L1 cache (#366 #380 #370 #369)
• Fix Pipeview (#432)

This version should be used with the following commit of Chipyard: https://github.com/ucb-bar/chipyard/commit/810db31abdb2bd38bd073856018c2d361ed0b6c8

This marks BOOM version 2.2.2. The significant change is deprecation of boom-template, to switch to the unified Chipyard development platform, which incorporates flows for RTL simulation, FPGA simulation through FireSim, and physical design through HAMMER. The process to design custom BOOM-based SoCs is greatly simplified.

Chipyard usage is very similar to boom-template. See the Chipyard docs for details. https://chipyard.readthedocs.io/en/latest/

Chipyard is still in ALPHA,

Changes:

• Integration of PNR head (#284)
• RoCC accelerator support (#333, #324, #261, #221)
• Support for heterogeneous system (#309, #278, #271)
• Allow non-power-of-2 core width (#314, #316, #312)
• 4-cycle fetch with improved fetch buffer (#359, #358, #308)
• Refactored, modularized rename and dispatch stages (#347, #327, #304)
• Numerous QoR fixes (#344, #343, #342, #341, #340, #335, #334, #330, #329)
• Fixes for MMIO loads and stores (#346, #297)
• Support for software breakpoints (#354)
• Chipyard compatibility (#306)
• June 2019 rocketchip (#305)

This version should be used with the following commit of Chipyard (from the master branch): https://github.com/ucb-bar/chipyard/commit/9d58818c2a9911d6db50eeb15e7e25e64090ee19

This marks BOOM version 2.2.1.

Changes:

• Deprecate unpipelined integer multiply
• Support RV32 BOOM
• Fix RVC for banked I$ configs
• Support no VM
• Clean up backend functional unit generation
• Support unified MEM and INT issue queues
• Fix FTQ clearing for flushes
• Other various RVC fixes
• Decouple load/store issue queue sizes
• Support wide floating point

This version should be used with the following commit of rocket-chip (from the master branch): https://github.com/freechipsproject/rocket-chip/commit/50bb13d7887e5f9ca192431234b057ae9d8edb6c

This version should be used with the following commit of boom-template (from the master branch): https://github.com/riscv-boom/boom-template/commit/427b21915c685cce7fcf520a1b889ad038eb003c

This marks BOOM version 2.2.0.

Changes:

• All configurations now support RISC-V compressed ("RVC") instructions
• PMP registers are enabled
• The NBDCache has been forked from rocket-chip
• Minor CSR instruction fixes
• ReadTheDocs documentation available at https://docs.boom-core.org/en/latest/
• CircleCI continuous integration
• Switch to Chisel3 syntax
• Updates for September 2018 rocket-chip

This version should be used with the following commit of rocket-chip (from the master branch): https://github.com/freechipsproject/rocket-chip/commit/50bb13d7887e5f9ca192431234b057ae9d8edb6c

This version should be used with the following commit of boom-template (from the master branch): https://github.com/esperantotech/boom-template/commit/1a0f9557f11d32f155ac17b9e3d4700d1dd69ad9

This marks BOOM version 2.1.1.

Changes:

• Support for integer-only configs
• Preliminary trace support
• Updates for July rocket-chip

This version should be used with the following commit of rocket-chip (from the master branch): https://github.com/freechipsproject/rocket-chip/commit/b8a67a41068b7f7bfe421c35b0cc613cdb2e6b50

This version should be used with the following commit of boom-template (from the master branch): https://github.com/esperantotech/boom-template/commit/27cfaf47c7e251b18690dc430143eb57f829cf12

This marks BOOM version 2.1.0.

Changes:

• Supports privileged spec v1.11-draft
• Speculative load wakeups
• Stable release for FireSim simulations. See https://fires.im/
• Boots Linux, runs SPEC, network-capable.

This version should be used with the following commit of rocket-chip (from the master branch): freechipsproject/rocket-chip@5d7a0e7

This version should be used with the following commit of boom-template (from the master branch): https://github.com/esperantotech/boom-template/commit/e8e93a1a1825567539de24b6aeead60ddf231a32

This marks BOOM version 2.0.1. Includes bug fixes to FPtoInt moves.

This version should be used with the following commit of rocket-chip (from the boom branch): https://github.com/freechipsproject/rocket-chip/commit/21cce2cd9a90630910f02bb0c936ca99b3a429f0

This marks BOOM version 2.0. BOOMv2 uses a distributed issue window; a split physical register file (separate integer and FP register files); and a 3-cycle fetch unit (+1 from BOOMv1). The pipeline length is configurable from 6 stages to 9 stages (fetch to integer ALU writeback). It implements RV64G and version v1.9 of the privileged ISA.

This version should be used with the following commit of rocket-chip (from the boom branch): https://github.com/freechipsproject/rocket-chip/commit/b3e9e363bb4335cb60f86856d096444842667b76

This marks BOOM version 1.0. BOOMv1 uses a unified issue window and a unified physical register file. It implements RV64G and version v1.9 of the privileged ISA.

This version should be used with the following commit of rocket-chip (from the boom branch): https://github.com/freechipsproject/rocket-chip/commit/41fe0d86cef4d91f5f62c26a149ef161c324a4b1