QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.
ISA: QNICE Instruction Set Architecture updated to version 1.6. The changes are:
PERFORMANCE: The new ISA leads to a speed increase of about 7% as documented
in q-tris_perf_test.asm
compared to the old ISA. The main reason is that
the new INCRB/DECRB only need two cycles compared to 4 cycles when switching
banks the old way. This leads to faster sub-routine calls.
MMIO: Cleaned up the MMIO address space and by doing so, changed all the locations of MMIO devices in sysdef.asm. This breaks binary compatibility with all software from version 1.5 and older, and therefore all this software needs to be reassembled and recompiled to run on version 1.6.
CPU: Updates to reflect the new ISA. Added interrupt system. And a comprehensive CPU test was added (test_programs/cpu_test.asm) and multiple CPU bugs were fixed both in the emulator and in the hardware.
MEGA65: Ported QNICE-FPGA to the MEGA65 (https://mega65.org/). This includes adding HDMI and HyperRAM support for the MEGA65.
TIMER INTERRUPT GENERATOR: Added. Is internally running on 100 kHz and contains two independent counters (see sysdef.asm for details).
INSTRUCTION COUNTER: Added. Counts all instructions executed by the CPU. Can be used for performance testing as shown in test_programs/q-tris_perf_test.asm and test_programs/mandel_perf_test.asm.
UART: Added a 32 Byte FIFO to the UART. This was necessary because the MEGA65 serial over JTAG does not support RTS/CTS and therefore we needed more stability. Now RTS/CTS should be unnecessary in most cases.
VHDL REFACTORINGS: The following system-wide refactorings have taken place with the goal to improve the code quality and the FPGA performance:
MONITOR: Disassembler can now handle the new ISA.
EMULATOR: Updated to reflect the new ISA.
EMULATOR: Usability improved: At the "Q>" prompt the emulator now displays the address from which the last instruction was read from. When an emulator run is interrupted by CRTL/C (SIGINT) the statistics page now also lists the last 16 addresses from which instructions were executed.
EMULATOR: Made the WebAssembly target compatible with Emscripten 1.39.14 (and newer and it still works with 1.39.10 and some of the older versions, but not with the versions in between). The background of this phenomenon is explained here: https://github.com/emscripten-core/emscripten/issues/10746
EMULATOR: Adjusted the standard emulation speed to 13.0 MIPS because this is the average Q-TRIS performance. Peak performance observed so far is in test_programs/mandel_perf_test.asm: 13.62 MIPS
Q-TRIS: Adjusted (slowed down) to match the CPU's speed increase by 7%.
TOOLCHAIN: Native assembler updated to reflect the ISA changes.
TOOLCHAIN: C code emitter and standard C library and Monitor library updated to reflect the MMIO changes. Standard C library recompiled to use register bank switching instead of the stack in all function calls.
TOOLCHAIN: qtransfer: Convenient mechanism for transferring software (.out files) from the host computer to QNICE-FPGA. Details: doc/README.md
TOOLCHAIN: Added support for Xilinx Vivado and made Vivado the main toolchain for our project. ISE is still supported though. Structured all hardware dependencies in the new folder 'hw' and added documentation in 'hw/README.md'.
TOOLCHAIN: Added Ubuntu Linux support, which means it should also run on any other Debian based distribution. You might want to install xclip for more convenience (.out copied to clipboard after assembler ran).
QBIN: All sample applications have been rebuilt due to changes in the ISA and the MMIO. A new download-link for the sample disk image is available: http://sy2002x.de/hwdp/qnice_disk_v16.img
DOCUMENTATION: Added:
This version greatly enhances the capabilities and the stability of the emulator. Detailed description: emulator/README.md
Hardware read-only support for SD Cards. Make sure to read the hints and constraints in doc/contraints.txt. To directly test the hardware without using the new Monitor libraries, use test_programs/sdcard.asm
Software read-only support for FAT32 (new Monitor Libraries sd_library.asm and fat32_library.asm).
Monitor: It is now possible to browse directories and to load/run files directly from the monitor. Partition #1 of the SD Card is automatically mounted when using directory or file related functions. New top level folder "qbin" contains demo programs that can be executed.
C Compiler, Standard C Library: VBCC toolchain including VBCC compiler, VASM assembler and VLINK linker: Stable basic C environment including file system access (via fopen, fread, ...) and including convenient editing functions due to the fact, that the Monitor's new versatile gets_slf() function is used when reading from stdin. Everything is located in the "c" subfolder.
Partition 1 of the SD Card is automatically mounted on-demand (upon first call of fopen). To test it, try c/test_programs/fread_basic.c
Monitor library is available, that wraps monitor functions. To test it, try c/test_programs/shell.c
EAE: Extended Arithmetic Element added: This is a 16-bit signed/unsigned integer multiplication (with 32bit results), division and modulo co-processor. An example of the impressive speedup can be seen in the source code comments of mandel_perf_test.asm, which shows a speedup of factor 4.5 compared with release version 1.3.
For testing it, use the following programs: test_programs/eae.asm test_programs/32bit-mul.asm
Further Library enhancements:
By default, version 1.1 behaves like version 1.0, i.e. input/output is done via UART, 8-N-1, 9.600 baud, RTS/CTS. But from version 1.1 on, you can now route the input via a PS/2 keyboard and the output via a 640x480 VGA monitor (80x40 characters):
Classic "Environment 1" (aka env1), inspired by the classic QNICE/A evaluation board environment. Features:
The package contains a working monitor application (version 0.2) including the mandelbrot demo application. Furtheron, the assembler and the emulator are included.
Feature complete QNICE CPU, original instruction set architecture (ISA V1.2) as of December 2007, is running on a simulated version of the QNICE/A evaluation board. Slighly enhanced TIL display (4 digits instead of two plus a mask register). Lower 32kB are ROM, upper 32kB are RAM. No UART, yet. For convenient simulation in ISIM, the amount of register bank is restricted to 16 and RAM to 256 bytes; just change env1_globals.vhd to get the full amount of RAM of the real QNICE/A and the full register file size of the QNICE CPU.