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Overview

The Earlgrey-PROD.M2 milestone stabilizes the feature set and architecture of Earlgrey and its IP blocks for the production tapeout. After this milestone, the focus shifts to the completion of security hardening and design verification. All hardware IP blocks have been signed off at least at the D2 and V1 development stages. IP blocks that have not had major changes since Earlgrey-ES tapeout have been signed off at D2S (or even D3) and V2S.

Major changes since Earlgrey-ES tapeout include:

• Architectural optimizations to reduce area (overview in #22025).
• Removal of the S&P layer from data scrambling of ROM and SRAMs (overview in #20788).
• Support for late debug enablement on DEV lifecycle devices (overview in #20829).
• Replacement of LFSR-based PRNGs by Bivium stream cipher primitives for masking countermeasures in AES and KMAC (overview in #19091).
• Interrupts from multiple HW IP blocks were changed from event type to status type to improve the programming model (overview in #15378).
• HMAC: Enabling SW context switching via save & restore (#21307) and additional digest modes (SHA-2 256/384/512) and key lengths (256/384/512/1024-bit) (#21604).
• I2C, SPI Device, and USBDEV: Multiple improvements and fixes to improve the programming model and increase standard compliance (details for each block below).
• SPI Device: Removal of generic mode to permit optimizations of the other modes (#20856).

Detailed Changelog

Earlgrey Top-Level Design

• The volatile raw unlock feature was disabled (#21372).
• The CC pins were changed to 5V-tolerant pad cells (#21695).
• The DFT strap pins were changed from IOC3 and IOC4 to IOR5 and IOR7, respectively (#21727).

FPGA Emulation

• Earlgrey was brought up on the CW340 (#19295).
• The base clock frequency on the CW310 was increased to 24 MHz (#19368).

ROM

• The retention SRAM was rearranged (#21587).
• The 64k ROM_EXT code size restriction was removed (#21831).
• ECDSA P256 support was added to the manifest (#21833).
• As part of moving root keys to OTP, the ROM key types were refactored (#21901), a module to load keys from OTP was added (#21902), and SPX+ keys were moved to OTP (#22066).
• The number of RSA keys was reduced to three to save ROM space (#22058).
• A naming bug in manifest extension getters was fixed (#22061).

adc_ctrl

• An issue related to sampling during low-power states was fixed, so that adc_ctrl does not accidentally get stuck in normal-power sampling mode while the chip remains in deep sleep (#21829).
• A FSM state observability CSR was added for debugging purposes (#21829)
• An interrupt with wakeup capability was added so that transitions from low power to normal power can be detected. This is mainly intended for debugging purposes (#21829).
• The single collated IRQ (which adc_ctrl generates from multiple internal sources) was converted from edge-based to level, so that SW doesn’t have to clear multiple IRQ status bits when handling an interrupt (#21872).

aes

• The implementation of the PRNG was changed from multiple LFSRs to the Bivium stream cipher to prevent brute-forcing attacks on the PRNG state (#19091).

aon_timer

• The size of the wakeup counter was increased to 64 bits (#21746).

clkmgr

• Clock buffers on all root clocks feeding into clkmgr was inserted to facilitate the hookup of on-chip clock controllers (OCC) (#21100).

csrng

• Microarchitectural optimizations to reduce area without functional impact (#22056, #22064).

edn

• The SW_CMD_STS CSR was reworked to fix and improve edn’s SW API (#20873).
• Microarchitectural optimizations to reduce area without functional impact (#21142).
• Not all recoverable alerts were sent to alert_handler, which was fixed (#21187).
• The handling of backpressure and status response from csrng was fixed, for which a new recoverable alert source (CSRNG_ACK_ERR status bit) and a new HW_CMD_STS CSR were added (#21142, #21280).

entropy_src

• The FIPS bit exposed to HW and SW was changed to SW-configurable (#21369).
• The 1-to-4 esbit packer was moved to after the health tests to streamline the hardware-based health testing in single-channel mode (#21626).The handling of backpressure in the internal pipeline and to the noise source was fixed (#21685 and #21799).
• The CSRNG AES halt request interface was fixed to reduce power spikes (#21787).
• Microarchitectural optimizations to reduce area without functional impact (#22041).

flash_ctrl

• The DIS CSR was changed from RW0C to RW1S (#20042).
• The microarchitecture was changed to share the scrambling module among flash banks (#22045, #22091, #22276).
• Four interrupts (prog_empty, prog_lvl, rd_full, rv_lvl) were changed to status type (#21226).

hmac

• Saving & restoring of the context (preliminary digest and message length), which allows SW to switch between different parallel message streams, was added (#21307).
• SHA-2 384 and SHA-2 512 were added (previously only SHA-2 256 was supported), along with integrating the SHA-2 multi-mode primitive into the HMAC (#21107), and the key length was made configurable between 128 bit, 256 bit, 384 bit, 512 bit, and 1024 bit (#21604).
• CSRs: The KEY CSR was extended to 32 32-bit registers, DIGEST CSR was extended to 16 32-bit registers, and the MSG_FIFO depth was extended to 1024 items (#21604). DIGEST_SIZE and KEY_LENGTH fields were added to the CFG CSR (#21604). HASH_STOP and HASH_CONTINUE fields were added to the CMD CSR (#21307).
• The fifo_empty interrupt was changed to status type (#21809).

i2c

• The READ field of the FDATA CSR was renamed to READB to prevent namespace collisions in DV code (#19721).
• The fmt_threshold and rx_threshold interrupts were changed to status type (#21621).
• Threshold interrupts were added for the target FIFOs (acq_threshold and tx_threshold) with status type (#21621).
• The fmt_overflow and tx_overflow interrupts were removed because they were not useful (#21621).
• The threshold configuration and level indicator CSR fields were extended to support up to 256-entry deep FIFOs (#21621).
• The fall time of SCL and SDA, tf, had been counted twice in the calculation of the clock pulse time, which was fixed (#21765).
• The depth of the ACQ FIFO was increased to 268 entries, so that the HW can absorb a max-length SMBus Block Write without SW intervention (#21789).
• Prediction of target clock stretching was added to the host-mode FSM, in order to align throughput with the timing parameters (#21813).
• A TXRST_ON_COND bit, through which SW can instruct the HW to automatically reset the TX FIFO if it observes a Stop or Repeated Start condition in target mode, was added to the TARGET_FIFO_CONFIG CSR (#21827).
• A TARGET_TIMEOUT_CTRL CSR, through which SW can limit the time for which the HW stretches SCL in target mode, was added (#21857). When HW reaches this timeout, it will NACK the byte and return to the idle state.
• The host FSM was changed to halt and stretch SCL upon receiving a NACK and only proceed once SW has acknowledged the resulting interrupt or a timeout expires, which SW can configure in the newly added HOST_NACK_HANDLER_TIMEOUT CSR and HOST_DISABLED_NACK_TIMEOUT bit in the STATUS CSR (#22049).
• The controller FSM was changed to reject a Start or Stop condition if SCL changes too soon after an SDA transition, in order to fix possible misbehavior when the hold time for SDA is 0 (#22106).
• The width of the TARGET_NACK_COUNT CSR was reduced from 32 to 8 bits because it had been overly wide (#22107).
• The storage microarchitecture of the FIFOs was changed from flip-flops to a single single-port SRAM (#22216) with 464 entries (#22232) to reduce area.

keymgr

• The valid signal for creator root key shares was split, so that each share now has its own valid signal (#20924).

kmac

• Issues around EDN timeouts were fixed (#19248).
• The masking of the Keccak core was improved and the PRNG was changed from an LFSR-based implementation to the Bivium stream cipher to prevent brute-forcing attacks on the PRNG state (#21624 and #22021).
• The fifo_empty interrupt was changed to status type (#21657).

lc_ctrl

• A CDC bug in lc_ctrl’s kmac interface was fixed (#19202).
• Transitions to the SCRAP lifecycle state are now allowed even if the maximum number of lifecycle transitions is reached (#21213).
• RMA acknowledge signals were changed from a daisy chain through multiple modules to one directly-connected signal per module (#21267).
• Diversification values were uniquified so that each of the TEST_UNLOCKED, DEV, and RMA lifecycle states now has a unique random netlist constant (#21372).

otbn

• Interpretation of the lc_rma_req and lc_escalate_en signals was fixed, to ensure that values other an On are interpreted as Off for non-escalation LC signals (#19628, #21272).
• The S&P layer was removed from data scrambling of the instruction and the data memory (#20855).
• Loop control was changed so that commit doesn’t factor into prefetch (#20957).
• Logic driving state_reset was simplified to ease timing (#20957).
• Instruction memory fetch logic for branches was reworked, primarily for X propagation reasons (#20957).
• Timing on instruction memory requests was improved by preventing errors from factoring into outputs of the instruction memory request (#20957).
• Timing on base register file data outputs was fixed (#20957).

otp_ctrl

• Substantial refactoring of the generation tooling for RTL and DV code without changing the functionality.
• A new OTP item, OWNER_SW_CFG_ROM_EXT_RECOVERY_EN, was added (#19133).
• The OWNER_SW_CFG_ROM_EXT_RECOVERY_EN OTP item was renamed to OWNER_SW_CFG_ROM_EXT_BOOTSTRAP_EN (#19209).
• Digest CSR and CSR read-enable assignments were made parametrizable (#20905).
• Support for SW partitions without a digest was added (#20905).
• Support for disabling integrity on a partition was added (#20905) and filters for ECC errors on them were added (#21256).
• The ERR_CODE CSR was changed to non-compact (#20905).
• Support for multiple HW_CFG partitions was added (#20906).
• An out-of-bounds error in the DAI (which was not hit before) was fixed and Xprop was fixed (#20906).
• Support for creator/owner seeds was added (#20924).
• The secret partition LC lock was made more generic (#20924).
• The offset of SW_CFG_WINDOW was changed from 0x1000 to 0x800 (#21040).
• The DAI registers were made software-lockable (#21059).
• The EN_ENTROPY_SRC_FW_READ and EN_ENTROPY_SRC_FW_OVER OTP fields were removed (#21118).
• A second HW_CFG partition was added and EnCsrngSwAppRead and EnSramIfetch were moved there (#21232).
• Two new SW partitions for ROM keys were added (#21270).

rom_ctrl

• The S&P layer was removed from data scrambling (#20855).

rv_core_ibex

• The SW_FATAL_ERR CSR was changed to RW1S (#20042).
• Encoding of register file addresses was changed to one-hot to improve fault injection resilience (lowRISC/ibex#2117).
• Lockstep enable was changed from a single-bit signal to a four-bit signal to improve fault injection resilience (lowRISC/ibex#2129).
• The S&P layer was removed from data scrambling of the instruction cache (lowRISC/ibex#2130).

rv_dm

• The option to enable debug late (i.e., after certain code has already run without debug access) in the DEV lifecycle was added (#21964).
• Tracking of non-debug-module reset completion was implemented (#22038).

sensor_ctrl

• An enable register for AST alerts (ALERT_EN) was added (#21870).

spi_device

• Generic mode was removed to permit optimizations of the flash and TPM modes (#20856).
• Divide SRAM into egress and ingress sections, with write-only and read-only software access, respectively (#20942).
• A 2-stage pipeline was added to break the combinational path for passthrough (particularly quad output) reads (#20966).
• Address mode synchronization was fixed (#21119).
• Synchronization of status bits was fixed (#21120).
• All timing mode CSRs were removed because spi_device now only supports mode 0 (#21161).
• TPM command handling was fixed, and read and write data were moved to the SRAM, with corresponding changes to the software interface (#21322).
• Separate constraints for TPM and fast passthrough were added (#21595).
• A mechanism to reset the flash read buffer was added (#21701).

spi_host

• The spi_event interrupt was changed to status type (#21278).
• A case of wrong status reported for the TX FIFO was fixed (#21325).
• Toggling of the TX line during Standard-mode RX-only segments was fixed (#22040).

sram_ctrl

• Synchronizers were added on LC/MuBi input signals (#19120).
• The S&P layer was removed from data scrambling (#20855).
• An RW1C status CSR for scrambling key rotation (SCR_KEY_ROTATED) was added (#20866).

sysrst_ctrl

• The IRQ synchronization mechanism was reworked and the IRQ was converted to status type (#21934).

uart

• The watermark interrupts (tx_watermark, rx_watermark) were changed to status type (#21632).

usbdev

• The implementation of the packet buffer was changed from a two-port to a single-port SRAM (#19857).
• The FSM was changed to truncate RX after receiving a PRE PID (#19195).
• Two CSRs (out_data_toggle and in_data_toggle) were added to save and restore IN and OUT data toggles to support resuming communications after deep sleep (#19269).
• Support for separate ‘Available Buffer’ FIFOs for regular OUT DATA packets and SETUP DATA packets being received by the device was added (#21229, #22181).
• The pkt_received, pkt_sent, link_resume, av_out_empty, and rx_full interrupts were changed to status type (#21237, #21607).
• Support for the safe retraction of IN packets was implemented (#21771, #21983).
• The fifo_ctrl CSR was added so that SW can reset the internal FIFO buffers (#21791).
• A bus_not_idle signal from the wakeup module to usbdev was added (#22019).
• Diagnostic and performance counters were added (#22118).

Overview

This is the EarlGrey Engineering Sample release candidate. All blocks are at least at D2.5 design stage, and V2.5 verification stage (except for RV_DM, USBDEV, PWM and PATTGEN).

This release is associated with GitHub milestone: M2.5.2

D2.5 versus D3

D2.5 is strictly a subset of the D3 signoff criteria, including the following D3 checklist items:

1. Meets D2(S) signoff criteria
2. Meets D3 signoff criteria for the following items:
   1. TODO_COMPLETE
   2. LINT_COMPLETE
   3. REVIEW_RTL
   4. REVIEW_SW_CHANGE
   5. REVIEW_SW_ERRATA

D2.5 reviews were performed offline and are tracked in checklists available in OpenTitan.org internal documents.

V2.5 versus V3

V2.5 is strictly a subset of the V3 signoff criteria, including the following V3 checklist items:

1. Meets V2 or V2S signoff criteria
2. DESIGN_DELTAS_CAPTURED
3. ALL_TODOS_RESOLVED
4. TB_LINT_COMPLETE
5. PRE_VERIFIED_SUBMODULES
6. NO_ISSUES_PENDING

V2.5 coverage metrics are at V2S level, and thus not referenced in the list above. Signoff reviews were performed offline and are tracked in checklists available in OpenTitan.org internal documents.

Release Contents

Design

All IPs meet the D2.5 development stage requirements:

1. D3 (14 of 35): lc_ctrl, uart, otp_ctrl, sysrst, adc_ctrl, alert_handler, aon_timer, gpio, pinmux, rom_ctrl, rv_plic, rv_timer, sensor_ctrl, sram_ctrl
2. D2.5 (21 of 35): All other blocks

Design Verification

All IPs are at V2.5 level, except for the IPs which have a verification signoff waiver (USBDEV, RV_DM), or which are explicitly not required to fully work for the ES tapeout (PWM, PATTGEN).

The following section notes the progress that has been made towards the M2.5.2 goal.

1. V2.5 (31 of 35): usbdev, i2c, rv_dm, entropy_src, spi_device, spi_host, csrng, flash_ctrl, kmac, lc_ctrl, sysrst_ctrl, keymgr, edn, otp_ctrl, uart, tlul, otbn, sram_ctrl, rv_core_ibex, clkmgr, pwrmgr, rstmgr, adc_ctrl, alert_handler, aes, aon_timer, hmac, rom_ctrl, rv_timer, rv_plic, gpio, sensor_ctrl, pinmux
2. V1 (1 of 35): RV_DM
3. V0 (1 of 35): USBDEV
4. V2S (2 of 35): pwm and pattgen
   Note that PWM and PATTGEN are functionally not needed for ES, since the use cases under consideration do not make use of these blocks.

Block Level Issues

1. All block level issues assigned to M2.5.2 have been resolved.

Top Level Test Cases

1. All Chip-Level test cases assigned to M2.5.2 have been resolved.
2. All Test-Triage issues identified for M2.5.2 have been resolved.

Manufacturing

1. All Manufacturing test cases assigned to M2.5.2 have been resolved.

Integration Testing

The following integration tests have been implemented and are passing:

1. USB. Block level smoketest #18063. FPGA targeted testing.
2. SPI_HOST. FPGA targeted testing. #18640
3. SPI Passthrough. FPGA targeted testing #18320.
4. I2C host. FPGA targeted testing. #18639
5. I2C device. FPGA targeted testing #18541.

Coverage Assessment

All blocks are at the required 90% coverage level or above, with the exception of the following blocks:

1. RV_DM: (Pass rate) 71.67, (Coverage) 81.52
   1. Implications are known and mitigation strategies as documented in the M2 waiver document available in the opentitan.org partner domain.
   2. An updated waiver document will be available as part of the M2.5.2 milestone that focuses on DV closure.
2. USB_DEV: (Pass rate) 48.79, (Coverage) 76.36 3. Implications are known and mitigation strategies as documented in the M2 waiver document available in the opentitan.org partner domain. 4. An updated waiver document will be available as part of the M2.5.2 milestone that focuses on DV closure.

CDC and RDC Assessment

Static RDC analysis and dynamic CDC enablement in simulation have been worked on on a best effort basis. The current status is: \

• Static RDC at 30 setup errors, 870 analysis warnings and 29 analysis errors.
• Dynamic CDC: 39 out of 43 DV environments are enabled.

Static CDC analysis was clean a few days before the release, but has now regressed to 7 setup warnings and 67 analysis errors due to last minute fixes to the spi_device RTL and updates to the spi_device synthesis constraints. The static analysis environment has not been cleaned up as part of M2.5.2 due to resourcing and tooling constraints. However, dynamic CDC has progressed well and 39 of 43 simulation environments now use CDC randomization.

Known Issues

The following known issues will not be addressed in the design and will require software workarounds.

• [i2c] Unexpected data in ACQ FIFO after deep sleep wakeup #18510
  • This problem likely occurs due to the fact that sleep wakeup is very fast on the FPGA since power-up delays are not correctly modeled. Also, the I2C may actually latch data before it has been fully configured and enabled.
  • Workaround: as discussed on the issue, a FIFO reset after I2C configuration solves the problem.
• [adc_ctrl] Limitations in wakeup detection #18511
  • There is a chance that the adc_ctrl FSM transitions from the low-power sampling mode into the normal power sampling mode without waking up the rest of the system. This can happen if the filter thresholds match during low power, but not after transitioning into normal power mode, since the FSM currently has no way to fall back into low-power sampling mode.The FSM may hence get stuck in the normal power mode that consumes significantly more power.
  • Workaround: while the problem cannot be completely avoided, this issue can be mitigated by taking only one sample after transitioning into normal power mode.
• [spi_device] TPM interrupt for Write FIFO #15785
  • This is a feature request for adding interrupts based on FIFO fill-status. The feature could however not be implemented due to schedule constraints.
  • Workaround: software will have to work around this limitation and use a polling-based approach.
• [i2c] Potential frequency output mismatch #18492
  • The I2C frequency does not always match the configured values. Investigations are still ongoing, but a suspected root cause is that there is an issue with how the programmed cycle counties are translated into actual cycles in the I2C bock.
  • Workaround: the I2C still works - just the frequency is not accurate. Potential workarounds are to either use the I2C as is, or compensate for the wrong translation logic by programming cycle counts that adjust for the measured frequency offset.
• [usbdev] aon_wake maintains pull up assertion over VBUS disconnection #18562
  • Suggested RTL improvement to increase stability during disconnection/interruption to VBUS/SENSE while OT is in deep sleep.
  • Workaround: When software returns from Deep Sleep and discovers a Disconnection event, it should be aware that the host may or may not have spotted a disconnection, and thus introduce a deliberate disconnect period by ensuring that usbdev pull up is disabled before deactivating the aon_wake module. See Issue for more details.
• [SPI_Host] SPI Top level test - FPGA #15074
  • As documented here on that issue, there are currently no plans to test the muxed spi_host1 at the FPGA level for M2.5.2.
• [lc_ctrl] TAP required delay before JTAG commands after reset #18724
  • The life cycle TAP is not immediately available after reset, due to the boot sequence. I.e., the power manager first waits for OTP, LC to initialize first. If the device is in PROD* or DEV, the power manager also waits for the ROM_CTRL to complete its checks before sending the strap sampling request to the TAP selection logic in the pinmux. This means that connecting to the life cycle controller TAP may fail if attempted too early.
  • From a hardware perspective this behavior is as expected (hence this is not a bug). The agent intending to connect to the LC TAP should either
    • wait long enough for the chip to boot before attempting to connect via JTAG (delay for the ASIC is yet to be determined).
    • or alternatively, attempt to read out a known JTAG register such as the device ID in a polling loop. This method may require assertion TRSTN before any attempt.
• [lc_ctrl/top] Clean up life cycle endpoints #19058
  • This is a cleanup task that has been identified while reviewing the design.
• [pwrmgr/sram_ctrl] Use synchronizers on all LC signals #19051
  • We identified that not all life cycle signals in pwrmgr and sram_ctrl are properly synchronized with prim_lc_sync. For Earlgrey ES, this is not critical since:
    • pwrmgr has the same clock root as lc_ctrl, and hence the signals are synchronous
    • sram_ctrl is not used while lc_ctrl and otp_ctrl are initialized, and hence there is enough time for the signals to stabilize after initialization.
  • For PROD and other integrations, though, this should be cleaned up.
• [otbn] Fix OTBN usage of life cycle control signals #19050
  • OTBN escalates locally upon detecting invalid life cycle signal encodings. This does not follow the design guidance for life cycle signals that specifically notes that CDC stagger must be tolerated. The reason why this issue did not need an ECO was that the relevant signal happens to be driven by flash_ctrl which is in the same clock domain as OTBN, and hence this is not a real problem for the earlgrey configuration.
• 5 ECOs were implemented as part of M2.5.2:
  • [i2c] Remove SCL glitch when FMT FIFO empties mid-transaction #18764 #18810
  • [i2c,rtl] SDA should be driven high in advance of SCL for restarts #18721 #18729
  • [usbdev] Remove data toggle clear in suspend #18940 #18941
  • [rtl/spi_device] Add extra cycle for CDC in spid_addr_4b #19005 #19003
• [i2c] Hold off NACK detection until posedge SCL #19014 #19015

Difference Among Release Candidates

Only one release candidate available for this milestone.

Overview

This is the EarlGrey Engineering Sample release candidate. All blocks are at least at D2 design stage, and V2S verification stage (except for RV_DM, I2C, RV_DM).

This is a follow up to Earlgrey-M2.5.1-RC0. All M2.5.1 releases are associated with GitHub milestone: M2.5.1.

Changes since M2.5.1-RC0

• Several DV updates (targeting M2.5.2 release)
• Several ROM release readiness changes (targeting M2.5.2 release)
• Update SDC constraints for synthesis
  • [spi_device] SDC updates & Enhance pass-through rates for wider reads by pipelining the return path #11718
  • [syn] Async FIFO gray pointer timing constraints #13011
  • [top] Update interface timing constraints #18274
• ECOs:
  • [M2.5, ECO, I2C] Restart condition violates I2C Specification #18721

Full Changelog: https://github.com/lowRISC/opentitan/compare/Earlgrey-M2.5.1-RC0...Earlgrey-M2.5.1-RC1

Overview

This is the EarlGrey Engineering Sample release candidate. All blocks are at least at D2 design stage, and V2S verification stage (except for RV_DM, I2C, RV_DM).

This release is associated with GitHub milestone: M2.5.1

Notes on Block Level Status

This release uses the definition of intermediate milestones D2.5 and V2.5 to describe block level status above D2S and V2S. These definitions are only used within the context of this document, and are not intended to be used as an official OpenTitan milestone definition.

D2.5 versus D3

D2.5 is strictly a subset of the D3 signoff criteria, including the following D3 checklist items:

1. Meets D2(S) signoff criteria
2. Meets D3 signoff criteria for the following items:
   1. TODO_COMPLETE
   2. LINT_COMPLETE
   3. REVIEW_RTL
   4. REVIEW_SW_CHANGE
   5. REVIEW_SW_ERRATA

D2.5 reviews were performed offline and are tracked in checklists available to OpenTitan partners.

V2.5 versus V3

V2.5 is strictly a subset of the V3 signoff criteria, including the following V3 checklist items:

1. Meets V2 or V2S signoff criteria
2. DESIGN_DELTAS_CAPTURED
3. ALL_TODOS_RESOLVED
4. TB_LINT_COMPLETE
5. PRE_VERIFIED_SUBMODULES
6. NO_ISSUES_PENDING

V2.5 coverage metrics are at V2S level, and thus not referenced in the list above. Signoff reviews were performed offline and are tracked in checklists available to OpenTitan partners.

Release Contents

Design

All IPs meet the D2.5 development stage requirements:

1. D3 (14 of 35): lc_ctrl, uart, otp_ctrl, sysrst, adc_ctrl, alert_handler, aon_timer, gpio, pinmux, rom_ctrl, rv_plic, rv_timer, sensor_ctrl, sram_ctrl
2. D2.5 (21 of 35): All other blocks

Design Verification

All IPs are at V2(S) level or above, except for the IPs which had a verification signoff waiver at M2 (I2C, USBDEV, RV_DM).

Note that block-level verification tasks for V2.5 are not part of the M2.5.1 exit criteria, since the verification signoff will be done at M2.5.2. Nevertheless, the following section notes the progress that has been made towards the M2.5.2 goal.

1. V2.5 (13 of 35): flash_ctrl, kmac, keymgr, otp_ctrl, tlul, clkmgr, rstmgr, adc_ctrl, alert_handler, hmac, sensor_ctrl, pwrmgr, lc_ctrl
2. V1 (2 of 35): i2c, rv_dm
3. V0 (1 of 35): usbdev
4. V2S (19 of 35): All other blocks

Details for i2c

I2C was not at V2 for this release but it was very close to achieving it. Overall regression pass rates were over 90% however coverage wasn't up to V2 standards, in particular FSM coverage was low (~50%) and there were some unimplemented coverage points (The i2c_rd_wr_cg, i2c_scl_stretch_cg, i2c_timing_parameters_cg, i2c_cmd_complete_cg).

There was high confidence that the missing coverage points were being stimulated by existing tests and the functionality had been observed working during other DV work.

A detailed waiver and mitigation test strategy document for i2c is available to OpenTitan partners.

Details for rv_dm

A detailed waiver and mitigation test strategy document for rv_dm is available to OpenTitan partners. This released focused on improving top level test coverage for this block.

Details for usbdev

A detailed waiver and mitigation test strategy document for rv_dm is available to OpenTitan partners. This released focused on improving top level test coverage for this block.

Block Level Issues

1. All block level issues assigned to M2.5.1 have been resolved.

Top Level Test Cases

1. All Chip-Level test cases assigned to M2.5.1 have been resolved.
2. All Test-Triage issues identified for M2.5.1 have been resolved.

Manufacturing Readiness

1. All Manufacturing test cases assigned to M2.5.1 have been resolved.

Integration Testing

The following integration tests have been implemented and are passing:

1. USB. Block level smoketest #18063. FPGA targeted testing.
2. SPI_HOST. FPGA targeted testing. #18640
3. SPI Passthrough. FPGA targeted testing #18320
4. I2C host. FPGA targeted testing. #18639
5. I2C device. FPGA targeted testing #18541

CDC and RDC Assessment

Static RDC analysis and dynamic CDC enablement in simulation have been worked on on a best effort basis. The current status is:

• Static RDC at 30 setup errors, 870 analysis warnings and 29 analysis errors.
• Dynamic CDC: 24 out of 43 DV environments are enabled.

Static CDC analysis was clean a few days before the release, but has now regressed to 7 setup warnings and 67 analysis errors due to last minute fixes to the spi_device RTL and updates to the spi_device synthesis constraints. These regressions (mostly waiver cleanups) will be fixed as part of M2.5.2.

The following known issues will not be addressed in the design and will require software workarounds.

Known Issues

• [i2c] Unexpected data in ACQ FIFO after deep sleep wakeup #18510
  • This problem likely occurs due to the fact that sleep wakeup is very fast on the FPGA since power-up delays are not correctly modeled. Also, the I2C may actually latch data before it has been fully configured and enabled.
  • Workaround: as discussed on the issue, a FIFO reset after I2C configuration solves the problem.
• [adc_ctrl] Limitations in wakeup detection #18511
  • There is a chance that the adc_ctrl FSM transitions from the low-power sampling mode into the normal power sampling mode without waking up the rest of the system. This can happen if the filter thresholds match during low power, but not after transitioning into normal power mode, since the FSM currently has no way to fall back into low-power sampling mode.The FSM may hence get stuck in the normal power mode that consumes significantly more power.
  • Workaround: while the problem cannot be completely avoided, this issue can be mitigated by taking only one sample after transitioning into normal power mode.
• [spi_device] TPM interrupt for Write FIFO #15785
  • This is a feature request for adding interrupts based on FIFO fill-status. The feature could however not be implemented due to schedule constraints.
  • Workaround: software will have to work around this limitation and use a polling-based approach.
• [i2c] Potential frequency output mismatch #18492
  • The I2C frequency does not always match the configured values. Investigations are still ongoing, but a suspected root cause is that there is an issue with how the programmed cycle counties are translated into actual cycles in the I2C bock.
  • Workaround: the I2C still works - just the frequency is not accurate. Potential workarounds are to either use the I2C as is, or compensate for the wrong translation logic by programming cycle counts that adjust for the measured frequency offset.
• [usbdev] aon_wake maintains pull up assertion over VBUS disconnection #18562
  • Suggested RTL improvement to increase stability during disconnection/interruption to VBUS/SENSE while OT is in deep sleep.
  • Workaround: When software returns from Deep Sleep and discovers a Disconnection event, it should be aware that the host may or may not have spotted a disconnection, and thus introduce a deliberate disconnect period by ensuring that usbdev pull up is disabled before deactivating the aon_wake module. See Issue for more details.
• [spi_host] SPI Top level test - FPGA #15074
  • As documented here on that issue, there are currently no plans to test the muxed spi_host1 at the FPGA level for M2.5.2.
• [lc_ctrl] TAP required delay before JTAG commands after reset #18724
  • The life cycle TAP is not immediately available after reset, due to the boot sequence. I.e., the power manager first waits for OTP, LC to initialize first. If the device is in PROD* or DEV, the power manager also waits for the ROM_CTRL to complete its checks before sending the strap sampling request to the TAP selection logic in the pinmux. This means that connecting to the life cycle controller TAP may fail if attempted too early.
  • From a hardware perspective this behavior is as expected (hence this is not a bug). The agent intending to connect to the LC TAP should either
    • wait long enough for the chip to boot before attempting to connect via JTAG (delay for the ASIC is yet to be determined).
    • or alternatively, attempt to read out a known JTAG register such as the device ID in a polling loop. This method may require assertion TRSTN before any attempt.

Design Verification Coverage Assessment

All blocks are at the required 90% coverage level or above, with the exception of the following blocks:

1. PRIM_LFSR: (Coverage) 89.17
   1. Not a concern since close to 90%
2. PRIM_PRESENT: (Coverage) 75.95 2. Not a concern, since the modes used in comportable IPs are tested as part of the comportable IPs, and coverage is collected as part of the comportable IP testbenches.
3. RV_DM: (Pass rate) 71.67, (Coverage) 81.52 3. Implications are known and mitigation strategies as documented in the M2 waiver document are being worked on. 4. An updated waiver document will be available as part of the M2.5.2 milestone that focuses on DV closure.
4. USB_DEV: (Pass rate) 48.79, (Coverage) 76.36 5. Implications are known and mitigation strategies as documented in the M2 waiver document are being worked on. 6. An updated waiver document will be available as part of the M2.5.2 milestone that focuses on DV closure.

Regression Snapshot

Name	Passing	Total	Pass Rate	Coverage
TL_AGENT	50	50	100.00 %	-- %
ADC_CTRL	886	920	96.30 %	97.52 %
AES/UNMASKED	1538	1582	97.22 %	97.16 %
AES/MASKED	1540	1582	97.35 %	98.45 %
AON_TIMER	429	430	99.77 %	98.50 %
CLKMGR	960	960	100.00 %	97.63 %
CSRNG	1616	1670	96.77 %	92.90 %
EDN	679	680	99.85 %	94.37 %
ENTROPY_SRC	2470	2470	100.00 %	98.46 %
FLASH_CTRL	1257	1278	98.36 %	96.53 %
GPIO	850	870	97.70 %	99.61 %
HMAC	906	920	98.48 %	99.60 %
I2C	1670	1770	94.35 %	91.41 %
KEYMGR	1094	1110	98.56 %	97.86 %
KMAC/MASKED	1273	1290	98.68 %	97.06 %
KMAC/UNMASKED	1272	1290	98.60 %	95.09 %
LC_CTRL	985	1030	95.63 %	96.21 %
OTBN	531	575	92.35 %	98.69 %
OTP_CTRL	1339	1343	99.70 %	93.35 %
PATTGEN	517	520	99.42 %	98.81 %
PRIM_ALERT	79	80	98.75 %	95.19 %
PRIM_ESC	20	20	100.00 %	91.31 %
PRIM_LFSR	50	50	100.00 %	89.17 %
PRIM_PRESENT	50	50	100.00 %	75.95 %
PRIM_PRINCE	500	500	100.00 %	100.00 %
PWM	416	420	99.05 %	98.69 %
PWRMGR	1068	1070	99.81 %	97.91 %
ROM_CTRL	479	500	95.80 %	95.77 %
RSTMGR_CNSTY_CHK	10	10	100.00 %	95.87 %
RSTMGR	619	620	99.84 %	99.53 %
RV_DM	342	473	72.30 %	81.12 %
RV_TIMER	609	620	98.23 %	99.61 %
SPI_HOST	814	830	98.07 %	98.08 %
SPI_DEVICE	1772	1820	97.36 %	96.95 %
SRAM_CTRL/MAIN	1036	1040	99.62 %	94.26 %
SRAM_CTRL/RET	1039	1040	99.90 %	94.23 %
SYSRST_CTRL	910	932	97.64 %	98.27 %
UART	1310	1320	99.24 %	99.27 %
USBDEV	154	330	46.67 %	69.70 %
ALERT_HANDLER	847	850	99.65 %	99.66 %
XBAR_MAIN	873	900	97.00 %	96.73 %
XBAR_PERI	900	900	100.00 %	99.28 %
CHIP	2888	2901	99.55 %	96.82 %