Open Register Design Tool Versions Save

Updates:

Merge of sdnellen fork...

• update antlr rev to 4.5.3 in build.gradle
• changed reset field in xml output to add 0x hex prefix
• added py and c++ to test checks
• fix for legacy verilog loop iterator syntax in wrap module
• Fix to reflect correct reset name in coverpoints
• Fix to allow user-defined signals to be accessed in rhs of assigns within child instances
• added rdl enum element description to xml output
• fixes to test to correctly support cheader output and catch ordt exceptions
• refactored cheader output to correctly generate for replicated and hierarchical register sets

Known issues:

Info:

Requires java 1.8+ To run... java -jar Ordt-230719.01.jar

Note that Ordt.jar bundles the antlr 4.5 runtime jar (see http://www.antlr.org).

ANTLR_LICENSE.txt

Updates:

• changed format of generated sv interrupt bind output to use path rather than int in assert names
• added use_module_path_defines uvmregs output parameter. If false, auto-generated calls to set_rdl_address_map_hdl_path using path defines will not be included in the model
• added include_component_info boolean xml output parameter. If true, adds a component tag containing the rdl component id path for each instance that has a non-anonymous component id (issue #52)
• refactoring of systemverilog module classes
• added include_sequential_assign_delays systemverilog output parameter. If true (default) a pound 1 delay is included in sequential assign statements (issue #54)
• python driver model enhancements: - added ** default_tag_name** pydrvmod output parameter to override default tag used in model - added reg width and field reset values to model - added get_path_instance_list method to python model output
• fix for error when generating certain output types without systemverilog output (issue #57)
• fix for resetsignal generated systemverilog code (issue #58)
• add context to create() calls for UVM registers (pull request #60)
• added hwload rdl field parameter. If specified, will cause multiple fields to be assigned to specified constant values at the same time using a single common input signal.
• Added RTL_ONLY rtl field sub_category. If an rdl intr is tagged as RTL_ONLY, systemverilog output will be generated with interrupt logic, but the interrupt will not be added to generated interrupt bind file, nor will it be tagged as an interrupt in xml output
• fixed reset behavior of negedge/bothedge intrs in generated systemverilog (issue #61)

Known issues:

Info:

Requires java 1.7 To run... java -jar Ordt.jar

Note that Ordt.jar bundles the antlr 4.5 runtime jar (see http://www.antlr.org).

ANTLR_LICENSE.txt

Updates:

• fixes for handling of rdl user-defined properties applied to addrmaps (issue #46, issue #47)
• removed void cast in generated interrupt bind module - ncsim doesnt like
• fix to default regwidth handling (issue #48)
• fix for calculation of address size in external regfile/addrmap regions
• added field_data option for parallel external reg regions. Allows field rather than full register data to be used in external region
• added rep_level options for parallel external reg regions. Allows ancestor regset replication to be collapsed into a single external interface
• fix bug (introduced by issue #46 fix) so defined properties are correctly used in addrmaps as well as regfiles
• fix for address alignment messages in replicated regsets
• added wrapper_info command to inline rdl params parser which allows simple delay stages, inverters to be added in rtl wrapper
• added base_address_override uvmreg output parameter
• added native uvm_model_mode option (issue #49)
• added valid reference checking for rdl rhs assign elements
• modified systemverilog/verilog generaton to pass interrupt tree signals between cascaded decoders when generate_child_addrmaps is set
• added generate_iwrap_xform_modules sv output parameter. If false, inhibits generation of common modules used in the wrapper module transforms.
• updated grammar structure so a common extern parameter grammar is imported to rdl and ext parameter grammars so java packages are correctly added without gradle post-processing. Modified build.gradle to always generate antlr output of grammars so import dependencies are handled (issue #41). Also added generateEclipseGrammar task to move antlr generated files into eclipse package directory structure.
• fix for overlay option command line parsing (issue #50)
• added python driver model output (pydrvmod command option).

Known issues:

Info:

Requires java 1.7 To run... java -jar Ordt.jar

Note that Ordt.jar bundles the antlr 4.5 runtime jar (see http://www.antlr.org).

ANTLR_LICENSE.txt

Updates:

• made rdl property booleans case insensitive
• added support for instance array references in rhs of rdl property/signal assigns
• fixes for address generation in external regions and when using modulus regfile base addresses
• changed control parameter grammar to allow empty group brackets
• covergroup output (if include_default_coverage or rdl field coverage property specified) will now be generated in a separate module when generate_dv_bind_modules is set
• added include_addr_monitor systemverilog parameter. If true, adds address range inputs and monitor outputs to generated rtl that provide indication of a matching transactions
• added use_numeric_uvm_class_names uvmregs output parameter. If true, unique integers will be used to generate block and reg uvm class names rather than using catenated instance path.
• added uvm_mem_strategy uvmregs output parameter to allow selection of structure/api used for uvm_mem/uvm_vreg instances in generated model
• added mimic_reg_api uvm_mem_strategy option that allows same uvm_reg access api to be used for uvm_mem/uvm_vreg structures (with intermediate reduction in model footprint)
• updated rdl grammar to allow address increment after address modulus
• allow alt integer formats as rdl instance array indices (issue #44)
• fix for calculation of endaddress in cppmod ordt_addr_elem_array (pull request #45)
• added options to qualify interrupt display info in interrupt bind module by sub-category or rdl mask/enable state
• added warnings for registers having no fields or sw access defined
• fixes for handling of rdl user-defined properties applied to addrmaps (issue #46, issue #47)

Known issues:

• setting the min_data_size control parameter to a value other than 32 bits results in a change to the default register width (default should remain 32b, issue #48)

Info:

Requires java 1.7 To run... java -jar Ordt.jar

Note that Ordt.jar bundles the antlr 4.5 runtime jar (see http://www.antlr.org).

ANTLR_LICENSE.txt

Updates:

• update to jspec parser for MINOR* subcategories and grammar fixes
• moved to gradle build flow
• made ordt return non-zero code on exit with error (issue #33)
• fix for uvmregs hdl path using reuse_classes (issue #38)
• fix to generated counter rtl (issue #39)
• added ability to add interface/struct encaps to PARALLEL external register regions (issue #40)
• added parallel_pulsed processor i/f option - uses single pulse read/write indication vs level-active used in parallel option
• added separate_iwrap_encap_files systemverilog output parameter - writes interface/struct defines to separate files
• added keep_fset_hierarchy jspec output parameter - translates rdl defined fieldstructs into jspec fieldsets rather than collapsing these structures into fields with extended names
• added generate_dv_bind_modules and use_global_dv_bind_controls systemverilog output parameters - control generation of modules that can be bound to generated decoder/logic rtl for verification

Known issues:

Info:

Requires java 1.7 To run... java -jar Ordt.jar

Note that Ordt.jar bundles the antlr 4.5 runtime jar (see http://www.antlr.org).

ANTLR_LICENSE.txt

Updates:

• fix for reset and resetsignal property assigns (issue #26)
• added reset=na option to remove a field's reset if default is set
• added wrapper_info systemverilog (affects verilog output also) output parameter, which allows simple signal invert and sync stages to be added in wrapper module
• made -verilog output option visible
• added support for jspec user-defined parameters and translation to/from rdl user-defined properties
• added enum encode info to xml output (issue #31)
• added root_typedef_name, root_instance_name, root_instance_count jspec output parameters
• cleanup of counter next assign for woclr case (issue #28)
• syntax fix in rtl output for external regions with only 2 regs (issue #19)

Known issues:

Info:

Requires java 1.7 To run... java -jar Ordt.jar

Note that Ordt.jar bundles the antlr 4.5 runtime jar (see http://www.antlr.org).

ANTLR_LICENSE.txt

Prelim release - has bug in export of enums to xml (issue #31)

Updates:

• added default_rw_hw_access rdl input parameter which sets default hw=rw rather than hw=r for all fields
• added include_field_hw_info xml output parameter, which controls if rdl hw-related info will be included in generated xml
• fix for packing of nested rdl fieldstructs when fieldstructwidth is specified
• updated testbench generator to support parallel root decoder interfaces
• added nack_partial_writes systemverilog output option, which issues nack for writes of size less than target (rather than relying on check of returned transaction size)
• added support for selectable width write enable control on parallel decoder interfaces (issue #15)
• added regs_use_factory boolean uvmregs parameter to allow registers to use the factory in output model (issue #16)
• added a check for invalid field/fieldstruct bit ranges/widths (issue #17)
• fix for reuse_uvm_classes uvmregs output option (issue #23)
• added max_internal_reg_reps systemverilog parameter to control max replication count allowed for internal registers (issue #24)
• fix for systemverilog issue with back to back pio transactions using gated logic clock (issue #25)
• added ordt_viewer utility for viewing ordt-generated xml files

Known issues:

• external reg array with only 2 registers throws vlog compile error (issue #19)

Info:

Requires java 1.7 To run... java -jar Ordt.jar

Note that Ordt.jar bundles the antlr 4.5 runtime jar (see http://www.antlr.org).

ANTLR_LICENSE.txt

Test release