An experiment for building gateware for the axiom micro / beta using amaranth-hdl
Building Blocks & Tools for FPGA Design with Python & Amaranth HDL <https://github.com/amaranth-lang/amaranth>
__.
Mostly a place to experiment and figure out how to build things.
Also the incubator for the future AXIOM Beta camera gateware & the home of the current AXIOM micro gateware.
This repo contains:
Prototypes of the upcoming Amaranth data types PackedStruct
and Interface
(here called Bundle
) (in src/lib/data_structure/
)
A stream Abstraction with various building Blocks: (in src/lib/stream/
)
various Amaranth cores (in src/lib/
) for:
tools for gluing together SOCs (currently supports the Xilinx Zynq and JTAG based plattoforms) in src/soc/
Poster about the naps soc infrastructure <doc/NapsPosterFPGAIgnite2023.pdf>
__.platform definitions for both the AXIOM Beta and the AXIOM Micro in src/devices/
a variety of other smaller half-working experiments in src/experiments/
Installing