Issie with Summer additions as used in Autumn Term 2023

• Thanks to FYP students Yujie Wang (speed up Simulator) and Petra Ratkai (Verilog compiler)
• Thanks to the Summer UROP students:
  • Samuel Tan
  • Theo Gkamaletsos
  • Lu Ju
• Thanks to the unpaid but very productive Summer Issie Developer Community students
  • Luke Hedley
  • Lucas Ng
  • Constantin Kronbichler
  • Ilan Iwumbwe
• Thanks to HLP class of 2023 for the better auto-routing, rotate and scale, and other enhancements scheduled for next year
• Thanks to Tom Clarke for the new Wire auto-Separation module

v4.1.0

• Initial release includes all additions except new breadcrumb-based waveform selector (scheduled for v4.1.1 if it can be done in time).
• Curvy-style gates in the end did not get added. Doing them nicely with N-input gates was too much work, but is on roadmap.
• Very many additions from last year:
  • Improved UI for step simulation with back and forwards
  • Improved UI for top-level waveform simulation (consistent step simulation)
  • Improved auto-routing of wires with auto-separation - very little manual adjustment now needed
  • Add sheet to project function
  • Breadcrumbs for sheet selector that display design hierarch visually
  • Right-click context menus throughout draw block
  • Direct right-click navigation from custom components to sheets with "Back" button to return.
  • Simulation 17X faster than last year
  • New NC component and auto-hints to use it to close unused outputs.
  • Hint pane to highlight otherwise obscure features.
  • Custom component scaling via drag
  • Rotate and scale for multiple selected components
  • New components: mergeN and splitN
  • New components: logic gates can now have N inputs. Currently N <=4 for no good reasons. Will allow N <=16 v4.1.1.
  • Built-in demo designs
  • Improved Verilog compiler (not scheduled for production use yet)
  • Too many bug fixes to mention

Issie with Summer additions as used in Autumn Term 2023

• Thanks to FYP students Yujie Wang (speed up Simulator) and Petra Ratkai (Verilog compiler)
• Thanks to the Summer UROP students:
  • Samuel Tan
  • Theo Gkamaletsos
  • Lu Ju
• Thanks to the unpaid but very productive Summer Issie Developer Community students
  • Luke Hedley
  • Lucas Ng
  • Constantin Kronbichler
  • Ilan Iwumbwe
• Thanks to HLP class of 2023 for the better auto-routing, rotate and scale, and other enhancements scheduled for next year
• Thanks to Tom Clarke for the new Wire auto-Separation module

v4.1.1

• Fix bug on macos only that greys out all sheets when using Import Sheet

v4.1.0

• Initial release includes all additions except new breadcrumb-based waveform selector (scheduled for v4.1.1 if it can be done in time).
• Curvy-style gates in the end did not get added. Doing them nicely with N-input gates was too much work, but is on roadmap.
• Very many additions from last year:
  • Improved UI for step simulation with back and forwards
  • Improved UI for top-level waveform simulation (consistent step simulation)
  • Improved auto-routing of wires with auto-separation - very little manual adjustment now needed
  • Add sheet to project function
  • Breadcrumbs for sheet selector that display design hierarch visually
  • Right-click context menus throughout draw block
  • Direct right-click navigation from custom components to sheets with "Back" button to return.
  • Simulation 17X faster than last year
  • New NC component and auto-hints to use it to close unused outputs.
  • Hint pane to highlight otherwise obscure features.
  • Custom component scaling via drag
  • Rotate and scale for multiple selected components
  • New components: mergeN and splitN
  • New components: logic gates can now have N inputs. Currently N <=4 for no good reasons. Will allow N <=16 v4.1.1.
  • Built-in demo designs
  • Improved Verilog compiler (not scheduled for production use yet)
  • Too many bug fixes to mention

Issie with Summer additions as used in Autumn & Spring Term 2023

• Thanks to FYP students Yujie Wang (speed up Simulator) and Petra Ratkai (Verilog compiler)
• Thanks to the Summer UROP students:
  • Samuel Tan
  • Theo Gkamaletsos
  • Lu Ju
• Thanks to the unpaid but very productive Summer Issie Developer Community students
  • Luke Hedley
  • Lucas Ng
  • Constantin Kronbichler
  • Ilan Iwumbwe
• Thanks to HLP class of 2023 for the better auto-routing, rotate and scale, and other enhancements scheduled for next year
• Thanks to Tom Clarke for the new Wire auto-Separation module

v4.1.2

This fixes a number of minor bugs (everything found in Autumn term or before that). No new functionality for Spring; curly-style gates + better waveform selection will be delayed now till Summer. Sorry!

• fix bug that prevented import sheet on macos
• fix bug that crashes Issie if SplitN or MergeN size is reduced
• increase previously very low limit on gate inputs
• improve catalog hints & UI, and Properties UI, for SplitN, MergeN, Gates

v4.1.1

• Fix bug on macos only that greys out all sheets when using Import Sheet

v4.1.0

• Initial release includes all additions except new breadcrumb-based waveform selector (scheduled for v4.1.1 if it can be done in time).
• Curvy-style gates in the end did not get added. Doing them nicely with N-input gates was too much work, but is on roadmap.
• Very many additions from last year:
  • Improved UI for step simulation with back and forwards
  • Improved UI for top-level waveform simulation (consistent step simulation)
  • Improved auto-routing of wires with auto-separation - very little manual adjustment now needed
  • Add sheet to project function
  • Breadcrumbs for sheet selector that display design hierarch visually
  • Right-click context menus throughout draw block
  • Direct right-click navigation from custom components to sheets with "Back" button to return.
  • Simulation 17X faster than last year
  • New NC component and auto-hints to use it to close unused outputs.
  • Hint pane to highlight otherwise obscure features.
  • Custom component scaling via drag
  • Rotate and scale for multiple selected components
  • New components: mergeN and splitN
  • New components: logic gates can now have N inputs. Currently N <=4 for no good reasons. Will allow N <=16 v4.1.1.
  • Built-in demo designs
  • Improved Verilog compiler (not scheduled for production use yet)
  • Too many bug fixes to mention

Issie with Summer additions as used in Autumn & Spring Term 2023

• Thanks to FYP students Yujie Wang (speed up Simulator) and Petra Ratkai (Verilog compiler)
• Thanks to the Summer UROP students:
  • Samuel Tan
  • Theo Gkamaletsos
  • Lu Ju
• Thanks to the unpaid but very productive Summer Issie Developer Community students
  • Luke Hedley
  • Lucas Ng
  • Constantin Kronbichler
  • Ilan Iwumbwe
• Thanks to HLP class of 2023 for the better auto-routing, rotate and scale, and other enhancements scheduled for next year
• Thanks to Tom Clarke for the new Wire auto-Separation module

v4.1.3

• Fix: demo projects cannot be loaded under macos
• Fix: current sheet is not saved when importing a sheet
• Fix: new IssieStick ID

v4.1.2

This fixes a number of minor bugs (everything found in Autumn term or before that). No new functionality for Spring; curly-style gates + better waveform selection will be delayed now till Summer. Sorry!

• fix bug that prevented import sheet on macos
• fix bug that crashes Issie if SplitN or MergeN size is reduced
• increase previously very low limit on gate inputs
• improve catalog hints & UI, and Properties UI, for SplitN, MergeN, Gates

v4.1.1

• Fix bug on macos only that greys out all sheets when using Import Sheet

v4.1.0

• Initial release includes all additions except new breadcrumb-based waveform selector (scheduled for v4.1.1 if it can be done in time).
• Curvy-style gates in the end did not get added. Doing them nicely with N-input gates was too much work, but is on roadmap.
• Very many additions from last year:
  • Improved UI for step simulation with back and forwards
  • Improved UI for top-level waveform simulation (consistent step simulation)
  • Improved auto-routing of wires with auto-separation - very little manual adjustment now needed
  • Add sheet to project function
  • Breadcrumbs for sheet selector that display design hierarch visually
  • Right-click context menus throughout draw block
  • Direct right-click navigation from custom components to sheets with "Back" button to return.
  • Simulation 17X faster than last year
  • New NC component and auto-hints to use it to close unused outputs.
  • Hint pane to highlight otherwise obscure features.
  • Custom component scaling via drag
  • Rotate and scale for multiple selected components
  • New components: mergeN and splitN
  • New components: logic gates can now have N inputs. Currently N <=4 for no good reasons. Will allow N <=16 v4.1.1.
  • Built-in demo designs
  • Improved Verilog compiler (not scheduled for production use yet)
  • Too many bug fixes to mention

This is the alpha release of Issie with improvements from 2023 work. It is slightly less stable than Issie normally, but mainly is alpha because it is expected that new features from 2023 work will continue to be added over the Summer.

Binaries will be updated on this release, with new tags, till Issie is ready for the Autumn Term v4.1.0 production release. (NB binaries will be labelled 4.0.1 etc because 4.0.a.1 is not allowed - however Issie versions will be correct).

v4.0.a.14

1. Many UI improvements and bug fixes throughout
2. Web workers added and tested - but not yet used.
3. Built-in demo designs added

v4.0.a.13

1. fix Ctrl-W so it always works changing sheets
2. Misc UI improvements, tooltips, responsiveness.
3. Reduce unnecessary saving of sheets.

v4.0.a.12

1. Various fixes to multi-symbol rotate and scale
2. fix obscure bug in separation code
3. reduce separation so circuits do not need saving immediately after load

v4.0.a.11

1. Replace sheets menu by new breadcrumbs hierarchy with right-click ops.

v4.0.a.10

1. Added 3 & 4 input gates
2. Added "add sheet" function (NB some improvement is still expected for complex cases)
3. Added right-click context menus to draw block objects

Fixes:

• Custom symbol size change

v4.0.a.9

1. Increase default wire separation
2. Fix bug when dragging segments

v4.0.a.8

1. improve separation: do not separate close same-net segments
2. When dragging multiple segments, all segments move together

v4.0.a.7

1. Fix top-level rerouting command

v4.0.a.6

1. Various improvements to separation - it should now be almost perfect
2. Edit menu commands to invoke reseparation, or autoroute and separation.

v4.0.a.5

1. Fix squiggly wire artifacts in new-style wire routing and separation
2. Fix N-bit NOT display bug
3. Add hint to custom component port movement and scaling ops
4. Various small fixes

v4.0.a.4

1. Fix a serious bug preventing IOLabel from simulating which was introduced by https://github.com/tomcl/issie/commit/338f4b18d7ac54b702b3417eefe9f66f484ef563

v4.0.a.3 --- Contains IOLabel simulation bug - don't use

1. Add "not connected" component
2. Mend simulator bug regression introduced by https://github.com/tomcl/issie/commit/fdd56a7a8a7483f61e36943add75fb77b7f1f850

v4.0.a.2 --- Contains IOLabel simulation bug - don't use

1. Lots of internal changes
2. Make truth tables work
3. Verilog compiler + components added

v4.0.a.1

1. Add new (better) wire routing.
2. Add wire separation
3. Add multi-symbol scale and rotate

This is the alpha release of Issie with improvements from 2023 work. It is slightly less stable than Issie normally, but mainly is alpha because it is expected that new features from 2023 work will continue to be added over the Summer.

Binaries will be updated on this release, with new tags, till Issie is ready for the Autumn Term v4.1.0 production release. (NB binaries will be labelled 4.0.1 etc because 4.0.a.1 is not allowed - however Issie versions will be correct).

v4.0.a.9

1. Increase default wire separation
2. Fix bug when dragging segments

v4.0.a.8

1. improve separation: do not separate close same-net segments
2. When dragging multiple segments, all segments move together

v4.0.a.7

1. Fix top-level rerouting command

v4.0.a.6

1. Various improvements to separation - it should now be almost perfect
2. Edit menu commands to invoke reseparation, or autoroute and separation.

v4.0.a.5

1. Fix squiggly wire artifacts in new-style wire routing and separation
2. Fix N-bit NOT display bug
3. Add hint to custom component port movement and scaling ops
4. Various small fixes

v4.0.a.4

1. Fix a serious bug preventing IOLabel from simulating which was introduced by https://github.com/tomcl/issie/commit/338f4b18d7ac54b702b3417eefe9f66f484ef563

v4.0.a.3 --- Contains IOLabel simulation bug - don't use

1. Add "not connected" component
2. Mend simulator bug regression introduced by https://github.com/tomcl/issie/commit/fdd56a7a8a7483f61e36943add75fb77b7f1f850

v4.0.a.2 --- Contains IOLabel simulation bug - don't use

1. Lots of internal changes
2. Make truth tables work
3. Verilog compiler + components added

v4.0.a.1

1. Add new (better) wire routing.
2. Add wire separation
3. Add multi-symbol scale and rotate

This is the alpha release of Issie with improvements from 2023 work. It is slightly less stable than Issie normally, but mainly is alpha because it is expected that new features from 2023 work will continue to be added over the Summer.

Binaries will be updated on this release, with new tags, till Issie is ready for the Autumn Term v4.1.0 production release.

v4.0.a.1

1. Add new (better) wire routing.
2. Add wire separation
3. Add multi-symbol scale and rotate

This is the alpha release of Issie with improvements from 2023 work. It is slightly less stable than Issie normally, but mainly is alpha because it is expected that new features from 2023 work will continue to be added over the Summer.

Binaries will be updated on this release, with new tags, till Issie is ready for the Autumn Term v4.1.0 production release. (NB binaries will be labelled 4.0.1 etc because 4.0.a.1 is not allowed - however Issie versions will be correct).

v4.0.a.4

Fix a serious bug preventing IOLabel from simulating which was introduced by https://github.com/tomcl/issie/commit/338f4b18d7ac54b702b3417eefe9f66f484ef563

v4.0.a.3 --- Contains IOLabel simulation bug - don't use

1. Add "not connected" component
2. Mend simulator bug regression introduced by https://github.com/tomcl/issie/commit/fdd56a7a8a7483f61e36943add75fb77b7f1f850

v4.0.a.2 --- Contains IOLabel simulation bug - don't use

1. Lots of internal changes
2. Make truth tables work
3. Verilog compiler + components added

v4.0.a.1

1. Add new (better) wire routing.
2. Add wire separation
3. Add multi-symbol scale and rotate

This is the production release for DECA 2022/23. There have been a lot of UI changes and additions since last year. So even though it is not tagged beta we expect a few issues, but hope for nothing major.

Please post issues if you discover any problems, or things you wish were better!

Current: v3.0.11 - see below for changes

Version Change Notes

v3.0.11

• Bug Fix - simulation not advanced exception in waveform simulator when viewing ram
• Bug Fix - < 32 bit counter component in some circumstances creates a simulation exception
• Bug Fix - incorrect step simulator results for > 1000 steps

v3.0.10

• Bug Fix #268 - changing the name of wire labels now correctly changes circuit error status
• Feature. Radix selector is now displayed in step simulation with multi-bit viewers. (This was not true if there were no other multi-bit displays)
• Improve split/merge component descriptions so they highlight vertical flipping to put MSB at top.

v3.0.9

• Feature: allow _ in component and sheet names

v3.0.8

• Fix bug which crashes waveform viewer in some cases

v3.0.7

• Fix transient bug which causes waveforms to be blank
• Improve waveform viewer help text

v3.0.6

• Fix negative numbers display in sDec radix inside wave simulator
• Make value column width adjustable in wave simulator

v3.0.5

• Fix > 32 bit busses
• Improve waveform simulation display

v3.0.4

Features:

• Selected Truth tables can now be selected from selected components without also needing all internal connections
• Truth-table columns can be moved left or right (See #254)

v3.0.3

Bug fixes:

• fix #256
• fix #257

v3.0.2

Minor changes:

• Improve custom component auto-sizing based on ports positions and names
• Improve theme colors (small changes)
• Improve properties dialog focus

v3.0.2.beta1

• fix #249 (still published as v3.0.1)

v3.0.1

• Pull together all of the Summer work
• Final changes from v3.0.0
  • Make bus compare constant definitions multi-radix consistent with constant definitions
  • Add shifts by numbers on busses to Verilog language accepted for Verilog components
  • Close some minor bugs from issues

Major changes from 2021/2022 - initial release notes

The code is now 36K lines (from 20K last year).

• Better Schematic Editor - components can be rotated/flipped. Auto-routing works better and from any edge of a component. Manual routing combines with auto-routing smoothly. Smart snapping makes it easier to position components
• Better Custom Components. The symbols instantiating subsheets can now have ports moved to any side of component with drag-and-drop UI. Components can have size scaled.
• Sheets descriptions can now be added, This appears in Sheet properties window and info boxes on sheet menu for rapid exploration of designs
• New components and additional properties on old components, fill in gaps.
  • Counter (optional enable, load).
  • N bit Adder (optional Cin, Cout)
  • N bit Not gate, AND, OR.
  • 2, 4, 8 input MUX and 2,4,8 output DEMUX to match. 2-input MUX has inputs switchable in position relative to select.
  • Bus spreader (1 bit -> N bits)
• Verilog design entry. New editor window with great error messages allows combinational logic to be implemented as Verilog equations
• New Waveform Viewer
  • One thing contentious - no scroll bar!
  • Can select any waveform on any sheet while simulating
  • Designs can be edited (any sheet) while running simulation, and simulation refreshed with a single click to see changes
  • UI is now consistent with Step simulator
  • Non-zero values on inputs allowed: default values are used and these can be set from Input properties or from step simulator
  • Components and connections highlight hovering over wave names (if the sheet the wave is on is selected
  • New hierarchical waveform selector (we think it is better, an it scales to very large designs)
  • Progressive simulation means simulation time is less noticeable
  • Progress bars for long waits in simulation or waveform generation (if 100s of waveforms are selected slowing this down) make a better UI
• Update memory linking to files. Memories now have a decent UI for linking initial contents to files. File change auto-updates a design - and then single click in waveform simulator will show results of simulating with new data. Should help work in Spring
• Truth table generator
  • Can show whole sheet or any selected part
  • Provides binary truth tables, with don't cares to simplify
  • Provides algebraic truth tables with good simplification of algebraic expressions
• Minor negative - as result of algebraic evaluation the simulator is now about 30% slower than last year. A simulation overhaul with a much faster reimplementation is scheduled for 2023
• Issie Stick supported. A one-click UI interfaces to external open source synthesis software to put designs onto a purpose-built EEE FPGA board so they drive real hardware. This is still experimental but the basic functionality now works.

Pretty well all the feature requests from last year have been implemented as well as a lot of things that make the UI more consistent and ergonomic.

Integrate summer FYP work into Issie.

3.0.0beta.10

• new color themes
• new simulation and waveform generation with progress bars on waits > 300ms (adjustable)
• some bug fixing
• new components polished
• memories linked to files auto-update
• Issie stick integration

3.0.0beta.9

• Integrate new components: counter, bit spreader
• Make CIN, COUT ports on adder optional
• Make switching MUX2 inputs possible
• Change background
• Add descriptions to sheets
• Optionally scale height and width of custom components
• Improve wavesim geometry

3.0.0beta.8

• Highlight all connections, and all labels on wave name hover
• Push input defaults from input state in step simulator, add defaults to step simulator
• Small polishing to waveform simulator

3.0.0beta.7

• Mend waveform simulator bug preventing editing while running simulator
• Improve info boxes
• Add default values to inputs

3.0.0beta.6

• Remake waveform simulator UI consistent with step simulator
• Major refactoring to allow waveform selection and simulation across all design sheets (it is about optimal)
• Technical debt reduction (painful) around how simulator is used
• Fix waveform simulator HTML/CSS
• Many fixes and improvements to verilog components

3.0.0beta.5

• integrate new waveform simulator