This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum
A host for some Verilog-snippets written during Lab Sessions of Computer Architecture Course at BITS Pilani.
Consider giving it a ☆ if the repo helps you in any way
iverilog -o filename.vvp filename.v
vvp filename.vvp
initial
begin
$dumpfile("filename.vcd");
$dumpvars;
end
gtkwave filename.vcd
`include "modulename.v"
Lab# | Labsheet | notes | topic |
---|---|---|---|
1 | link | link | Intro to verilog |
2 | link | link | Combinational Circuit Modeling |
3 | link | link | Sequential Circuit Modeling |
4 | link | link | ALU Design |
5 | link | link | Register File Implementation |
6 | link | link | Single Cycle Datapath Design |
7 | link | link | Multi-Cycle controller Design |
8 | link | link | Pipeline Design |