HDL libraries and projects
Changelog
Supported tools version for this release are:
Changes in 2022_r2 Patch1:
Known issues: a. Versal based carriers (vck190) might not boot with 2022_r2 Patch1 image.
The problem appears because some revisions of VCK190 or VPK may have the date/time set randomly or in 64bit format. To make them boot, it is enough to overwrite the date, following next steps:
Another workaround is to boot it with GRHD files provided by Xilinx (doesn't matter if it's petalinux or yocto), and after is booting to type next commands:
date -s "$(wget -qSO --max-redirect=0 google.com 2>&1 | grep Date: | cut -d' ' -f5-8)Z" & hwclock --systohc
After reboot, you should be able to boot also with Kuiper official image.
b. Video output may not work. There are two scripts that can be run in Kuiper terminal: enable_dummy_display.sh - which is used to create a display for zynq based boards and fix_x11.sh - which is used to create display for zynqmp based boards. Running the one for zynq on a zynqmp device or vice versa will broke video output. The solution is to delete the wrong created file if there exists (/usr/share/X11/xorg.conf.d/xorg.conf is created by enable_dummy_display.sh and /etc/X11/xorg.conf is created by fix_x11.sh).
c. SysID value returned by dmesg during booting may be older that the last commit from this branch. This is expected since HDL projects are not recompiled if there are no changes that affects them. Also, for Arria10 SOC sysid value is expected to not be returned.
Reference links: HDL Testbenches repository Linux repository Kuiper repository NO-OS repository SD Card image
Xilinx Vivado 2022.2 Quartus Prime Pro Edition 22.4 Quartus Prime Standard Edition 21.1* *Quartus Standard 21.1 is used only for Cyclone5 projects (C5SOC Kit and DE10 nano)
Projects added:
ad411 on Zed (only No-OS support)
Projects removed (you can find pre-built files in previous releases or main):
ad9265_fmc on zc706
ad9434_fmc on zc706 (the project still remained in main)
ad9739a on zc706
cn0501 on coraz7s (the project still remained in main)
dac_fmc_ebz on a10soc (the project still remained in main)
fmcadc2 on vc707 and zc706
fmcadc5 on vc707
imageon
adrv9361z7035 and adrv9364z7020 on ccpackrf
Versal based carriers (vck190) won't boot with 2022_r2 Kuiper image
The workaround is to boot it with GRHD files provided by Xilinx (doesn't matter if it's petalinux or yocto), and after is booting to type next
commands:
date -s "$(wget -qSO --max-redirect=0 google.com 2>&1 | grep Date: | cut -d' ' -f5-8)Z"; hwclock --systohc; poweroff
Afterwards, it should boot also with Kuiper official image.
cn0506 mii/rmii hang during booting, on zynq platforms, if both ethernet ports are connected to the network. If there is rgmii, zynqmp platform or ports are not both connected, the setup will boot fine.
The problem is already fixed and is part of latest boot files. To get it, is enough to run 'adi_update_boot.sh' from inside a 2022_r2 Kuiper.
Video output may not work. There are two scripts that can be run in Kuiper terminal: enable_dummy_display.sh - which is used to create a display for zynq based boards and fix_x11.sh - which is used to create display for zynqmp based boards. Running the one for zynq on a zynqmp device or vice versa will broke video output. The solution is to delete the wrong created file if there exists (/usr/share/X11/xorg.conf.d/xorg.conf is created by enable_dummy_display.sh and /etc/X11/xorg.conf is created by fix_x11.sh).
SysID value returned by dmesg during booting may be older that the last commit from this branch. This is expected since HDL projects are not recompiled if there are no changes that affects them. Also, for Arria10 SOC sysid value is expected to not be returned.
Xilinx Vivado 2021.2 Quartus Prime Pro Edition 21.4 Quartus Prime Standard Edition 20.1.1* *Quartus Standard 20.1.1 is used only for Cyclone5 projects (c5soc and de10nano)
Projects that are not writing bitfile on FPGA, just booting Kuiper: zynq-zed-otg adv7513_de10nano
New projects on zcu102: ad9695_fmc ad9081_fmca_ebz_x_band ad9081_fmca_ebz_x_band-vcxo100 ad9081_fmca_ebz_x_band-vcxo100-direct-clk ad9081_fmca_ebz_x_band-direct-clk
New projects on adrv9009zu11eg_adrv2crr: fmcxmwbr1 clockdist
New projects on coraz7s: ad719x_asdz cn0561 cn0579
New projects on Zed Board: ad777x_ardz adaq8092_fmc cn0561 cn0577 ad7768-4
New projects on de10nano: ad777x_ardz cn0579
cn0506 project got simplified. Now it's one single HDL project that can be built with parameters for different variations:
make INTF_CFG=RGMII (default value),
make INTF_CFG=MII or
make INTF_CFG=RMII
Projects removed from 20212_r2 release; please use them from previous release or master: ad_fmclidar1_ebz on zc706 cn0506_rgmii on a10soc all projects based on a10gx
2021_R2 will be the last release for next projects: ad9739a_fmc on zc706 imageon on zed adrv9361z7035 on ccpackrf adrv9364z7020 on ccpackrf
On Arria10 SOC with cn0506_mii, IPs are not assigned on both ports even if dhcp is enabled.
Video output may not work. There are two scripts that can be run in Kuiper terminal: enable_dummy_display.sh - which is used to create a display for zynq based boards and fix_x11.sh - which is used to create display for zynqmp based boards. Running the one for zynq on a zynqmp device or vice versa will broke video output. The solution is to delete the wrong created file if there exists (/usr/share/X11/xorg.conf.d/xorg.conf is created by enable_dummy_display.sh and /etc/X11/xorg.conf is created by fix_x11.sh).
SysID value returned by dmesg during booting may be older that the last commit from this branch. This is expected since HDL projects are not recompiled if there are no changes that affects them. Also, for Arria10 SOC sysid value is not returned from dmesg log (dmesg | grep sysis)
I. Adding support for:
II. Suporting ad908x on multiple carriers and add examples built with different JESD configurations:
On Arria10 SOC with cn0506_mii, IPs are not assigned on both ports even if dhcp is enabled.
Video output may not work. There are two scripts that can be run in Kuiper terminal: enable_dummy_display.sh - which is used to create a display for zynq based boards and fix_x11.sh - which is used to create display for zynqmp based boards. Running the one for zynq on a zynqmp device or vice versa will broke video output. The solution is to delete the wrong created file if there exists (/usr/share/X11/xorg.conf.d/xorg.conf is created by enable_dummy_display.sh and /etc/X11/xorg.conf is created by fix_x11.sh).
axi_spi_engine, jesd204 (Multiple fixes and improvements)
axi_ad6676, axi_ad9963, axi_adc_decimate, axi_adc_trigger, axi_generic_adc, (Fixes and improvements)
axi_ad7616 (Update ad_edge_detect port names)
axi_ad9739a (Add tristate option for ad_serdes_out)
axi_dac_interpolate (Export signals indicating the rate)
axi_i2s_adi (Create xgui files)
spi_engine (Add pulse_width and pulse_period registers)
util_adcfifo (Update interfaces for the asymetric memory)
util_pack (Add support for 64 channels)
New library:
Add support for next:
Next projects are failing. You can use them from older releases:
Kuiper image does not extend to the capacity of SD Card Workaround: This happens when first use of a new created SD card is on a development board. If you see that the root fs partition is not extended to the SD card capacity minus 1 GB (fixed size of boot partition), just open a terminal and type
raspi-config --expand-rootfs
Sometimes .RBF file is not seen even if it exists in boot partition root Workaround: When there are too many files/folders in the BOOT drive on the SDcard it seems that the bootloader get confused. Delete some unused files should fix this issue, or delete everything on the BOOT drive and let only socfpga_arria10_socdk.rbf, socfpga_arria10_socdk_sdmmc.dtb and zImage.
Gnuradio gives a pop-up error when try to open it from Menu. Workaround: gnu radio can be opened from terminal by typing:
export PYTHONPATH=$PYTHONPATH:/usr/local/lib/python3/dist-packages
ldconfig
axi_spi_engine, jesd204 (Multiple fixes and improvements)
axi_ad6676, axi_ad9963, axi_adc_decimate, axi_adc_trigger, axi_generic_adc, (Fixes and improvements)
axi_ad7616 (Update ad_edge_detect port names)
axi_ad9739a (Add tristate option for ad_serdes_out)
axi_dac_interpolate (Export signals indicating the rate)
axi_i2s_adi (Create xgui files)
spi_engine (Add pulse_width and pulse_period registers)
util_adcfifo (Update interfaces for the asymetric memory)
util_pack (Add support for 64 channels)
New library:
Add support for next:
Supported tools version for this release are:
Major updates:
Supported tools version for this release are:
Major updates:
Library updates:
New projects:
Reference links:
*EXCEPTIONS: All the projects, that are using ZCU102 development platform, should be built with Vivado 2018.3, this is for the users owning a zcu102 rev1.1 starting from label 0432055-05. Due to an end of life of the DDR4 SODIMM part on the ZCU102 Evaluation Kit. The new memory requires different settings during the FSBL. Starting with Vivado 2018.3, when targeting a ZCU102 board, the FSBL will have a custom function to query the SPD prom on the DIMM to determine which DIMM is being used. This is described in:
Supported tools version for this release are:
Major updates:
Library updates:
New projects:
Reference links:
Note: The A10GX based projects may fail from time to time, as the synthesizer, router and mapper may not find a valid configuration. In case this happens, try regenerating the design with reduced address width for the ADC/DAC BRAM FIFOs.
*EXCEPTIONS: All the projects, that are using ZCU102 development platform, should be built with Vivado 2017.2, simply because Vivado 2016.4 does not support the production version of the FPGA (xczu9eg-ffvb1156-2-i).