Adjustments made based on build changes in dependencies
No support given for environment-specific installation issues in the instructions
GDSII file input and simulation file input
Support for all 7 standards-compliant GDSII file elements
Must state physical extents in each Cartesian dimension, the frequency sweep, the bottom z-coordinate and height and relative permittivity of each layer, and the coordinates of each port (must only have a single coordinate differ between source and return) along with the port direction in the simulation input file
Capable of handling a logarithmic or linear frequency sweep of any reasonable number of points
RAM limitations generally prevent more than 10 ports at this time and discretization smaller than manufacturing tolerances
SPICE subcircuit file output of all linear components
SPICE subcircuit file meant to be used with Sandia Xyce
Alternative: SPEF file output without ability to consider nonlinear effects or DC biasing in post-simulation
Notice: Output files with circuit-based representations are presently limited in validity only to narrowband signals about the lowest frequency
Essential solver capability for Z-parameter output
Able to report Z-parameters, Y-parameters, or S-parameters in Keysight CITIfile or Touchstone file formats
Notice: inductive and high-frequency effects omitted in present release (only RC-behavior included)
User must supply transistor model and identify ports defined for each I/O pin and each transistor of interest
The post-simulation step uses Sandia Xyce to combine the SPICE subcircuit, transistor models, and port excitation signals to run arbitrary circuit simulations of the system with large-signal effects and biasing
Performance changes since v0.1-beta:
More timing information printed to terminal
Overhauled parasitics matrix representation and handling
Reduction of objects in fdtdMesh class
Faster point-in-polygon algorithm implementation and more stable when run in polygons and circles
Less reliant on unordered_map
Faster generation of nullspace solutions in dielectric region and conductor region
Experimentation with repository structure and compiler optimization in makefile recipes
Does not support array references, mirroring, magnification, or rotation in the GDSII file
Must state physical extents in each Cartesian dimension, the frequency sweep, the bottom z-coordinate and height and relative permittivity of each layer, and the coordinates of each port (must only have a single coordinate differ between source and return) along with the port direction in the simulation input file
SPICE subcircuit file output of all linear components
SPICE subcircuit file meant to be used with Sandia Xyce
Alternative: SPEF file output without ability to consider nonlinear effects or DC biasing
Essential solver capability for Y-parameter output
User must supply transistor model and identify ports defined for each I/O pin and each transistor of interest
The post-simulation step uses Sandia Xyce to combine the SPICE subcircuit, transistor model, and port excitation signals to run arbitrary circuit simulations of the system with large-signal effects and biasing