Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
This project contains fully pipelined floating-point FFT/IFFT cores for Xilinx FPGA, Scheme: Radix-2, Decimation in frequency and decimation in time;
Integer data type and twiddles with configurable data width.
Code language - VHDL, Verilog
Vendor: Xilinx, 6/7-series, Ultrascale, Ultrascale+;
License: GNU GPL 3.0.
Title | Universal floating point FFT cores (Xilinx FPGAs) |
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Author | Alexander Kapitanov |
Project lang | VHDL, Verilog |
Vendor | Xilinx: 6/7-series, Ultrascale, US+ |
Release Date | 02 Feb 2015 |
Last Update | 27 Jun 2019 |
Floating point 23-bit vector (optimized for FPGAs):
A = (-1)^sign(A) * 2^(exp(A)-31) * mant(A)
FFTs:
Butterflies:
Math (in fp23):
Delay line:
Twiddles:
Buffers:
FFTs:
Buffers: