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HAL – The Hardware Analyzer

v4.2.0

11 months ago

GUI plugin manager
- WARNING: modified plugin core API - reduced number of base classes and instead added extension components
- added overview of loaded plugins and their features
- added interactive buttons to load and unload plugins
- added feature to load plugin automatically if needed for file parsing
- prevent unloading of plugin if it is needed as a dependency of another plugin
- changed plugin load policy to have only mandatory or user required plugins loaded at startup
Boolean functions
- added BooleanFunction::substitute(const std::map<std::string, std::string>&) to substitute multiple variable names at once
- changed BooleanFunction::get_constant_value to return std::vector<BooleanFunction::Value>, thereby removing the 64-bit limit
- added BooleanFunction::Node::get_constant_value, BooleanFunction::Node::get_index_value, and BooleanFunction::Node::get_variable_name
- added BooleanFunction::get_constant_value_u64 and BooleanFunction::Node::get_constant_value_u64 to retrieve the constant value as u64 if it comprises less than 64-bit
- added BooleanFunction::has_constant_value(const std::vector<BooleanFunction::Value>&) and BooleanFunction::Node::has_constant_value(const std::vector<BooleanFunction::Value>&)
- added BooleanFunction::algebraic_printer as an alternative printer for BooleanFunction::to_string to print a Boolean function in algebraic form
- added shift and rotate operators Shl, Lshr, Ashr, Rol, and Ror
plugins
- boolean_influence
  - added deterministic variants of all Boolean influence functions that shall be used for Boolean functions with only few input variables
  - added additional parameters for more control to the subcircuit and gate variants of get_boolean_influence
- netlist_preprocessing
  - added decompose_gates_of_type and decompose_gate that decompose combinational logic gates into basic gate types
  - added parse_def_file to parse a Design Exchange Format file that contains placement information
  - simplify_lut_inits now annotates the original init string into the data container
- verilog_parser
  - added annotation of all net names that where merged during parsing in the data container
  - added implicit wire declarations for assign statements
  - changed the behavior of the parser when flattening a netlist and generating new unique names (instead of appending an index we now add a prefix containing the names of parent modules)
- z3_utils
  - added compare_netlists function that functionally compares two netlists that only differ in their combinational logic
  - removed class z3Wrapper
  - renamed to_z3 to from_bf and added support for missing node types
  - renamed to_hal to to_bf and added support for missing node types
  - changed to_cpp to output only the C++ code implementing the Boolean function and nothing more
- dataflow_analysis
  - added API to interact with dataflow analysis results from C++ and Python
  - added automatic creation of pin groups for data and control pins of register modules
  - added parameter to only write or retrieve information on certain register groups
  - deprecated plugin_dataflow::execute as its functionality is now split between dataflow::analyze and the members of dataflow::Result
  - removed file writes if not explicitly called by user
- netlist_simulation_controller
  - added versions of add_waveform_group taking a module pin group as input
  - added versions of set_input taking a WaveData object, vectors of nets and values, a WaveDataGroup and a vector of values, and a module pin group and a vector of values as input
- solve_fsm
  - changed both versions of fsm_solving to now not only consider data inputs of the state register, but also synchronous control signals.
- xilinx_toolbox
  - added the first version of the xilinx_toolbox plugin that provides functionality especially fitted to xilinx fpga netlists
decorators
- added NetlistModificationDecorator
  - added delete_modules to delete all (or a filtered subset of) the modules in a netlist
  - moved replace_gate from netlist_utils, now returns pointer to replacement gate
  - added connect_gates to connect two gates at the specified pins via a new or already existing net
  - added connect_nets to merge two nets into one, thereby connecting them
- BooleanFunctionDecorator
  - added a version of get_boolean_function_from that takes a module pin group as input
selection details widget
- added Focus item in graph view to several context menus
- added Isolate in new view to gate/module related context menus
- changed Isolate in new view policy for modules: open exclusive module view if such a view already exists
- improved drag&drop functionality to move module pins and merge module pin groups
miscellaneous
- added Gate::get_modules to recursively get all modules that contain the gate by traversing the module hierarchy
- added Net::is_a_source(const Gate*) and Net::is_a_destination(const Gate*) that check whether a gate is a source/destination independent of the gate pin
- added PinGroup<T>::contains_pin to check whether a pin is part of the respective gate or module pin group
- added overloaded version of deserialize_netlist that takes a gate library, thereby overruling the gate library path in the .hal file
- added utils::wrapped_stoull and utils::wrapped_stoul that wrap the standard string to integer conversion and use hal::Result<> for error handlung instead of exceptions
- added utility function is_valid_enum to check whether the string representation of an enum value is valid.
- added serialization of physical gate positions (non-negative integer)
- added keyboard shortcuts for fold, unfold, and remove from view
- added filter parameter to get_fan_[in/out]_[nets/endpoints]
- added pyBinds for the LogManager class
- added pyBinds for the ProjectDirectory class
- added Module::move_pin_group to change the order of pin groups of a module
- changed abort being more responsive when aborting layouting of large views
- changed and improved color scheme for light style
- changed labels on HAL startup screen to better resemble the new project structure
- removed toolbox from groupings widget
bugfixes
- fixed build from tarball
- fixed minor navigation bugs on settings page
- fixed missing Python bindings for GatePinGroup
- fixed SolveFsmPlugin not properly replacing power and ground nets in Boolean functions
- fixed searchbar attempting time consuming search when there is no content to search
- fixed some documentations of core functions
- fixed igraph not building anymore by relaxing irgaph compiler options
- fixed Python GUI API being unavailable at runtime
- fixed nets without source or destination not being shown when unfolding the module they belong to in the selection details widget
- fixed cmake failing to parse HAL version number from file
- fixed pins and pin groups not being hashable in Python
- fixed Python script execution abort button disappearing when switching tabs
- fixed segfault when deleting a module for which an exclusive view exists
- fixed not loading all plugins if the GUI is not in control
- fixed Verilog writer not being a dependency of Verilator plugin

v4.1.0

1 year ago

selection details
- module icons reflect module color
- gate icons shape according to gate type
- user setting to adjust size of or omit icon in upper right corner
project import/export
- added export feature: generate zipped project including external gate libraries and python source files
- added import feature by extracting zipped project
- added quazip library sources (deps) since recent distributions no longer link binary packages against qt5
netlist parsers
- added (limited) support for 'defparam' statements to Verilog parser
- added support for pin assignments by order instead of name to Verilog and VHDL parser
GUI comments
- user can add comments to gates and modules to take notes on the reverse engineering progress
- comments are shown in the graph view (as little notes on the gate/module boxes) and in the selection details widget
plugin netlist_preprocessing
- collection of utility functions preparing a raw netlist for further analysis
- remove LUT fan-in endpoints that do not show up in the LUT's boolean function via remove_unused_lut_inputs
- remove buffer gates via remove_buffers, also dynamically by analyzing Boolean function and connected inputs
- remove redundant gates via remove_redundant_logic, i.e., gates of equal type with identical inputs
- remove unconnected gates/nets via remove_unconnected_gates and remove_unconnected_nets
- simplify LUT configuration strings based on constant inputs via simplify_lut_inits
plugin bitorder_propagation
- propagate a known order of input/output pins within module pin groups to other connected modules
decorators
- BooleanFunctionDecorator
  - substitute power and ground nets/pins by constant values in Boolean functions via substitute_power_ground_nets and substitute_power_ground_pins
  - get a concatenated Boolean function corresponding to a vector of nets or Boolean functions via get_boolean_function_from`
- BooleanFunctionNetDecorator
  - get a unique Boolean function variable for a net via get_boolean_variable and get_boolean_variable_name
  - get the net corresponding to a unique Boolean function variable via get_net_from
  - get the net ID corresponding to a unique Boolean function variable via get_net_id_from
- SubgraphNetlistDecorator
  - copy a subgraph of the netlist via copy_subgraph_netlist
  - get the Boolean function of a subgraph via get_subgraph_function
  - get the inputs to the Boolean function of a subgraph without computing the Boolean function via get_subgraph_function_inputs
miscellaneous
- added functions get_pin_names, get_input_pins, get_input_pin_names, get_output_pins, and get_output_pin_names to class Module
- added function BooleanFunction::get_truth_table_as_string that returns the truth table of a Boolean function as a formatted string
- added missing GND, VCC, and RAM gate types to the ICE40ULTRA gate library
- added Python bindings for the HAL project manager
- added new GUI dialog for creating an empty project (without providing a netlist)
- changed all example netlists to be HAL projects
- API cleanup for plugin solve_fsm
bugfixes
- fixed Verilog and VHDL parser ignoring pin order of modules
- fixed order of module pins in Verilog writer
- fixed some errors in the Python documentation
- fixed pin types of power and ground gate types in various gate libraries
- fixed spamming the log with messages related to module pins
- fixed segfault that sometimes occurred when deleting a module
- fixed saving absolute paths for Python files and not copying them to the new project folder when using Save as...
- fixed some project manager bugs related to inaccessible files
- fixed missing Python binding for GateType::get_pin_groups
- fixed incorrect undo action for "fold parent module"
- fixed some internal data structure of the Verilog and VHDL parsers not being cleared after each instantiation attempt
- fixed wrong gate type properties for MUX gates in various gate libraries
- fixed net and instance aliasing in VHDL and Verilog parser
- fixed netlist parser bug related to unconnected module pins that are being directly assigned to another wire/signal in the module/entity body
- fixed get_pins returning pins in wrong order if no filter is specified

v4.0.1

1 year ago

WARNING: this release breaks multiple APIs, please make sure to adjust your code accordingly.
project manager
- added keeping all data belonging to a netlist in a single project directory
- added import of Verilog and VHDL netlists as well as existing .hal files into new projects
- added referencing all project files with relative filenames so that project can be ported to different location (whenever possible)
- added CLI option -p to open existing project
- changed CLI option -i import netlist to new project
netlist simulation
- added interactive waveform viewer to the HAL GUI
- added new netlist simulation backend with out-of-the-box support for Verilator
- added easy integration of additional simulation engines by writing respective wrapper functionality
- added support for reading Saleae traces as simulation input to allow simulation on real-world inputs
- added tools to list, dump, compare, and export simulation results directly from disk
- added interaction between waveform viewer and GUI so that simulated net states can be visualized in netlist
- deprecated custom HAL simulator, which is now only available for debugging purposes
Boolean functions
- added entirely new Boolean function architecture based on reverse Polish notation
- added new SMT solver interface with out-of-the-box support for both z3 and Boolector
- added custom symbolic execution engine
- added improved Boolean function optimization based on ABC
module and gate pins
- added a new system for gate and module pins, breaking all previously used APIs
- added GatePin class to keep properties of gate pins stored within gate types
- added ModulePin class to keep properties of module pins stored within modules
- added PinGroup class to collect related pins in a dedicated container
- added pin related interactions to GUI actions (undo and macro feature, log in crash dump)
selection details widget
- added tabs to unclutter the presented information
- added more details on gate/module pins
- added more details on LUT functionality
- added options to edit properties such as names, types etc. whereever applicable
running Python interpreter in background thread
- added option to abort Python script execution from within the GUI
- added support for input and raw_input functions for Python scripts to take input from the HAL Python console
- added GUI widgets to query for strings, numbers, file names, modules, or gates from Python scripts
python console and editor features
- changed to using PEG instead of PyParser to parse whether statement is complete if python version >= 3.9
- added automatically saving all Python editor tabs upon saving the entire project (even un-named tabs)
- added timer to display abort button if Python console command runs for more than 5 seconds
GateTypeProperty additions
- changed gate type properties carry, buffer, lut, and mux to c_carry, c_buffer, c_lut, and c_mux
- added new gate type properties such as c_and, c_or, ... to better represent combinational logic
- added pin types carry and sum to better annotate pins of gate types with property c_carry, c_half_adder, or c_full_adder
- added respective annotations to gate libraries shipped with HAL
miscellaneous
- added context menu entry to add any module or gate to cone view
- added link feature between entry in module tree view and graphical view, e.g. renaming the module will also rename the view
- added GUI API for plugins so that plugins can query for input parameter and execution can be triggered by push button
- added Gate::get_init_data and Gate::set_init_data for simplified access to the INIT data of, e.g., LUT type gates
- changed HGL gate library format to better support new gate pin features (backward compatible)
bugfixes
- fixed gate locations not being properly loaded from a gate's data fields
- fixed multiple memory leaks
- fixed rare segfault when adding gates to a module
- fixed segfault when removing the last item from a view
- fixed parsing of Liberty gate library attribute clock
- fixed description of flip-flops and latches in all FPGA gate libraries

v3.3.0

2 years ago

WARNING: this release partially breaks the GateType API, please make sure to adjust your code accordingly.
added user action system to enable recording and reverting actions within the GUI
- moved most GUI actions to the new user action system, including interactions with the graph view and view management
- user actions can be recorded and exported as a macro file allowing easier debugging and crash reporting
- recording of the user actions is automatically dumped on crash
- users can now revert actions executed within the GUI
rebuild the settings system from scratch to allow for easier integration of new settings
- theme setting (and many others) can now be changed during the session
- added a warning when attempting to assign a keybinding that is already in use
- added incremental search for settings
- added setting to enable/disable extra window to list all executed instances from UserAction
added new Move to module ... dialog
- allows to create new module or select from existing modules
- existing modules can be selected from a table, tree-view, or using a module picker within the graph view
- enables searching for existing modules
- added cursor to indicate that user is in module pick mode
added successor / predecessor utilities to gate and module context menu
- shortest path between two gates can be highlighted or added to current view
- predecessors or successors can be highlighted or added to the current view up to a user-specified depth
- different grouping colors can be assigned depending on the distance from the origin
- common predecessors or successors can be found and added to view
improved layouter
- omit repeated layouting during an ongoing activity
- show progress bar during layouting
- allow user to abort layouting
- preserve graph view location of gate when moving it to new module
- fixed routing errors for complex cable swaps
- fixed multiple connections of a single net to the same gate not being shown properly
- fixed incorrect placement of new gates and modules in cone view when navigating starting from a net
added generic SMT solver interface.
- added translation from BooleanFunction to SMT-LIB.
- added BooleanFunction::Node data structure to extend functionality to generic ASTs.
- added support for z3 and boolector SMT solvers.
- added cpp-subprocess library to handle communication with SMT solver.
- added Boost Spirit x3 library to generate grammar-based parser from SMT-LIB models to C++ data structures.
improved handling of properties for special gate types such as LUTs and FFs.
- properties that only apply to special gate types have been moved out of the GateType class and into a designated GateTypeComponent
- added functions to retrieve a gate type's components based on some filter condition
- added special components dealing with RAM properties
improved netlist parsers
- split VHDL and Verilog parsers into two independent plugins
- netlist parsers now take the path to the netlist file as input instead of a std::stringstream
- added support for Z and X assignments to Verilog and VHDL parsers
- added tri as a synonym for wire to the Verilog parser
- fixed netlist parsers assigning wrong order of inputs for some multi-bit signals
improved netlist writers
- netlist writers now take the output path as input instead of a std::stringstream
- removed broken VHDL writer (will not be supported until further notice)
- entirely new Verilog writer that respects module hierarchies
- added GEXF netlist writer, e.g., for netlist analysis within Gephi
expanded netlist_utils
- added function get_common_inputs to get inputs that are common across multiple gates
- added function replace_gate to replace a gate with an instance of another gate type
- added function get_gate_chain and get_complex_gate_chain to find gates that are arranged in a chain
- added function get_shortest_path to compute the shortest path between two gates
- added function get_next_gates to get the predecessors or successors of a gate up to a user-specified depth
- added function get_partial_netlist to export parts of a netlist as a netlist instance
dataflow_analysis plugin
- can now take groups of flip-flops as input that should not be touched during analysis
- this is meant to aid the dataflow analysis by passing control registeres identified beforehand, which prevents them from being merged into the datapath
new internal event system
- binds event handlers to a netlist instance
- facilitates listening to the events of selected netlists only
improved search
- all searchbars now come with options for "Exact Match" and "Case Sensitive" search, as well as a "Clear" button
- added search icons to the Python editor and the module widget
- disabled the search filter whenever the searchbar is not visible within a widget
miscellaneous API changes and additions
- added function is_top_module to class Module to determine whether a module is the top module
- added function get_nets to class Module to get all nets that are connected to any of the gates or submodules of a module
- added functions is_gnd_net and is_vcc_net to class Net to determine whether a net is connected to GND or VCC
- added functions operator== and operator!= to classes Netlist, Gate, Net, Module, and Endpoint
- added Python bindings for netlist_serializer
miscellaneous GUI changes and additions
- added Save As... option to save .hal files under a different name
- added Export ... menu to export the netlist using any of the registered netlist writers
- added Remove from view action to context menu for gates and modules
- added context menu options to close multiple view tabs at once
- added an indicator showing whether views have been modified
- added HAL version number to the info shown in About
- added Fold parent module option to module context menu
- when trying to create a view for a module that is already associated with an (unchanged) view, the existing view is activated instead of creating a new view
bugfixes
- fixed selection details not being updated immediately when renaming or changing a type
- fixed navigation bug where ports and nets did not match for modules
- fixed list of navigation targets containing duplicates and/or loops
- fixed drag'n'drop bug related to negative coordinates
- fixed liberty parser aborting on unknown pg_type
- fixed stylesheets
- fixed improper handling of GND and VCC nets within the solve_fsm plugin
- fixed module port names not being freed when reassigned a new name
- fixed segfault when no VCC or GND gate is present within a netlist

v3.2.6

3 years ago

added support for multiple properties (formerly refered to as "base type") for a single instance of class GateType
- renamed enum GateType::BaseType to GateTypeProperty and moved it out of class GateType
- added function has_property to class GateType
- changed function get_base_type of class GateType to get_properties
- changed HGL gate libraries to support multiple properties
- changed function create_gate_type of class GateLibrary to support multiple properties
added sequential, power, ground, buffer, mux, and carry gate type properties to enum GateTypeProperty
moved enums PinType and PinDirection from class GateType into global scope
added get_path to netlist_utils to retrieve all gates on the predecessor/successor path from a start gate/net to gates of a specified property
made optimize_constants of class BooleanFunction publicly accessible
refined buffer removal in netlist_utils::remove_buffers to take constant 0 and 1 inputs into account
added high-impedance state Z to class BooleanFunction and added basic support to evaluate
cleaned up and refined some logger outputs and streamlined log channel names
disabled extended logging again
changes to z3_utils (WIP)
fixed crash related to GraphicsScene destructor
fixed overlapping gates in cone view (and subsequent segfault) by suppressing gate coordinates when adding to cone view
fixed get_gate_by_id and get_gates of class Netlist returning only gates contained within one of its modules (causing a GUI crash upon deleting gates from a module)
fixed nets of old module not updating when moving gate from one module to another

v3.2.5

3 years ago

WARNING: temporarily enabled extended logging (includes taking screenshots) for university course purposes. Note that no data leaves your machine unless you actively provide it to us.
views get persisted to .halv file and are restored if the file is found on disk
fixed bug in boolean_influence plugin causing problems on global inputs
fixed gate details widget not showing full list of pins for large gates

v3.2.4

3 years ago

added plugin boolean_influence that enables calculation of the boolean influence for each FF depending on the predecessing FFs
extended the z3_utils plugin with a z3Wrapper class, which holds exactly one z3::expr and the corresponding z3::context
removed the code coverage checks from the macOS pipeline and added test command, so the macOS pipeline will work again properly
fixed a bug in DANA, where sometimes the net names were output in the DANA results instead of the gate names

v3.2.3

3 years ago

fixed z3_utils plugin being disabled by default causing linking errors
fixed load_initial_values and load_initial_values_from_netlist assigning values to potentially non-existing nets

v3.2.2

3 years ago

refactored gate library handling
- separated gate library manager from gate library parser interface
- added gate library writer interface to enable writing out gate library files
extended and refactored gate library functionality
- added create_gate_type to class GateLibrary to enable gate type creation from Python
- added mark_vcc_gate_type and mark_gnd_gate_type to class GateLibrary to enable marking gate types as power or ground connections
- added get_gate_type_by_name and contains_gate_type_by_name to class GateLibrary
- added pin types and respective functions to GateType to enable assigning special-purpose pins
- added get_gate_library to class GateType
- added base types ram, dsp, and io
- merged input and output pin groups to simplify pin group handling
- removed add_gate_type function from class GateLibrary
- removed GateTypeSequential and GateTypeLut classes and moved their functionality into class GateType
- renamed some functions to have shorter and more understandable names
added new gate library format: "HAL Gate Library" (HGL)
- supports assignment of pin types to gate types
- added parser for HGL (.hgl) files
- added writer for HGL (.hgl) files
refactored liberty gate library parser
- added parsing of power and ground pins (pg_pin) to Liberty parser
added more netlist utility functions
- added get_nets_at_pins to retrieve nets that are connected to a vector of pins
- added remove_buffers to remove buffer gates from a netlist
- added remove_unused_lut_endpoints to remove unused LUT fan-in endpoints
- added rename_luts_according_to_function to rename LUTs depending on the Boolean function they implement
added to_z3 to class BooleanFunction to translate a Boolean function into a z3 expression
added highly experimental solve_fsm plugin for FSM verification using z3
added z3_utils plugin to provide common z3 functions to all other plugins
improved layouter uses location information from gate API
switched from float gate coordinates to integer ones
the netlist simulator VCD writer now optionally takes a set of target nets to write to VCD
fixed add_boolean_function of class Gate assigning wrong functions to LUTs
fixed wrong Python binding for property gate_library of class Netlist
fixed netlist simulator segfaulting when an output pin of a FF remains unconnected
fixed optimization of Boolean functions sometimes producing wrong or non-optimal results
fixed netlist_utils::get_subgraph_function returning wrong results if input pins without relevance for the Boolean function remained unconnected
fixed layouter not showing connections if things change within submodules by adding additional test whether removing or adding a gate/module requires context update

v3.1.11

3 years ago

added highly experimental way to close and reopen netlists at runtime
- known issue: the Python context does not change properly between netlists
added creation of backups for Python files created within the editor outside of the .hal file
added user prompt when detecting Python file backups after a crash
fixed crash when moving top module upward
fixed module cache inconsistencies causing bad memory allocs in the GUI when deleting nets or endpoints