Digital Versions Save

A digital logic designer and circuit simulator.

v0.30

1 year ago
  • Added a search function
  • Added a presentation mode.
  • Adds Q and CTRL-Q hotkeys to copy the component the mouse pointer is hovering over.
  • Now there is resetRandom method available in the test code to reset the random number generator used by the random function.
  • The remote server is now disabled by default. It must be enabled in the settings.
  • When a new component has been placed with CRTL click, you can place another one.
  • Fixes the ignored default value in demuxer HDL export.

v0.29

2 years ago
  • Allows loading byte base files in big-endian format.
  • Added some more DIL chips
  • Tunnel now shows signal state
  • Fixes tutorial dialog positioning issue
  • Fixed some issues with 7489 and 74189
  • Fixed a bug in the LUT component that caused difficulties when generic code was executed.
  • Fixed an issue in the seven segment persistence of vision implementation.
  • Fixed a Verilog generation issue when using filenames that contain spaces.

v0.28

2 years ago
  • Inputs and outputs can have a smaller shape.
  • Added paste functionality to ROM data editor.
  • Added an rle encoding for storing rom content, which can result in smaller dig files.
  • Added some more ATF150x devices
  • Probe is able to count edges.
  • Italian translation was added, special thanks to Luca Cavallari
  • Added an external component that is based on a file instead of storing the code in the component itself.
  • Fixed an issue with clicking on tightly placed components.
  • Allows variable sample size in default data graph.
  • Added an option to skip certain sub-circuits in HDL creation. This allows the user to use a handwritten HDL implementation of the sub-circuit.

v0.27

3 years ago

v0.26.1

3 years ago

v0.26

3 years ago

v0.25

3 years ago

v0.24

4 years ago

v0.23

4 years ago

v0.22

5 years ago