Cortex M Versions Save

Low level access to Cortex-M processors

v0.7.7

1 year ago

What's Changed

Full Changelog: https://github.com/rust-embedded/cortex-m/compare/v0.7.6...v0.7.7

v0.7.6

1 year ago

v0.7.6 - 2022-08-12

  • Added critical-section-single-core feature which provides an implementation for the critical-section crate for single-core systems, based on disabling all interrupts. (#448)

v0.7.5

1 year ago

Deprecated

  • the ptr() function on all peripherals register blocks in favor of the associated constant PTR (#386).

Changed

  • The inline-asm feature no longer requires a nightly Rust compiler, but does require Rust 1.59 or above.

Fixed

  • Fixed singleton!() statics sometimes ending up in .data instead of .bss (#364, #380). (Backported from upcoming 0.8 release).

v0.7.4

2 years ago

v0.7.4 - 2021-12-31

Added

  • Added support for additional DWT counters (#349)
    • CPI counter
    • Exception overhead counter
    • LSU counter
    • Folded-instruction counter
  • Added DWT.set_cycle_count (#347).
  • Added support for the Cortex-M7 TCM and cache access control registers. There is a feature cm7 to enable access to these (#352).
  • Add derives for serde, Hash, and PartialOrd to VectActive behind feature gates for host-platform use (#363).
  • Support host platforms besides x86_64 (#369).
  • Added delay::Delay::with_source, a constructor that lets you specify the SysTick clock source (#374).

Fixed

  • Fix incorrect AIRCR PRIGROUP mask (#338, #339).
  • Fix nightly users of inline-asm breaking now that the asm macro is removed from the prelude (#372).

Deprecated

  • DWT::get_cycle_count has been deprecated in favor of DWT::cycle_count. This change was made for consistency with the C-GETTER convention. (#349)

v0.7.3

2 years ago

[v0.7.3] - 2021-07-03

Fixed

  • Fixed compilation for native targets on non-x86 host systems (#336, #337).

Added

  • The Delay struct now offers direct delay_us() and delay_ms() methods without having to go through the embedded-hal traits (#344).

v0.7.2

3 years ago

Fixed

  • Fixed a bug where calling asm::delay() with an argument of 0 or 1 would underflow, leading to a very long delay.

v0.6.7

3 years ago

v0.6.6

3 years ago

Fixed

  • Fixed missing ITM reexport on thumbv8m.base targets.

v0.7.1

3 years ago

Added

  • New assembly methods asm::semihosting_syscall, asm::bootstrap, and asm::bootload.

Deprecated

  • msp::write has been deprecated in favor of asm::bootstrap. It was not possible to use msp::write without causing Undefined Behavior, so all existing users are encouraged to migrate.

Fixed

  • Fixed a bug in asm::delay which could lead to incorrect codegen and infinite loops.
  • Improved timing guarantees of asm::delay on multiple-issue CPU cores.
  • Additional compiler fences added to inline assembly where necessary.
  • Fixed DWARF debug information in pre-built assembly binaries.

v0.7.0

3 years ago

Added

  • New InterruptNumber trait is now required on interrupt arguments to the various NVIC functions, replacing the previous use of Nr from bare-metal. For backwards compatibility, InterruptNumber is implemented for types which are Nr + Copy, but this will be removed in a future version.
  • Associated const PTR is introduced to Core Peripherals to eventually replace the existing ptr() API.
  • A delay driver based on SysTick.
  • You can now use LTO to inline assembly calls, even on stable Rust. See the asm/lib.rs documentation for more details.
  • Initial ARMv8-M MPU support
  • ICTR and ACTLR registers added
  • Support for the Security Attribution Unit on ARMv8-M

Changed

  • Previously, asm calls without the inline-asm feature enabled used pre-built objects which were built by a GCC compiler, while inline-asm enabled the use of llvm_asm! calls. The asm system has been replaced with a new technique which generates Rust static libs for stable calling, and uses the new asm! macro with inline-asm. See the asm/lib.rs documentation for more details.
  • Cache enabling now uses an assembly sequence to ensure correctness.
  • ptr() methods are now const.

Breaking Changes

  • SCB::invalidate_dcache and related methods are now unsafe, see #188
  • Peripherals struct is now non-exhaustive, so fields may be added in future non-breaking changes
  • Removed aligned dependency
  • Removed const-fn feature
  • Removed previously deprecated APIs
    • NVIC::clear_pending
    • NVIC::disable
    • NVIC::enable
    • NVIC::set_pending
    • SCB::system_reset
  • Removed basepri, basepri_max, and faultmask registers from thumbv8m.base