A hardware implementation of CNN, written by Verilog and synthesized on FPGA
This project is an attempt to implemnt a harware CNN structure.
The code is written by Verilog/SystemVerilog and Synthesized on Xilinx FPGA using Vivado.
The code is just experimental for function, not full optimized.
Only 4 elementary modules implemented:
A LeNet is constructed using the 4 elementary modules, the weights and biases are hard coded in ROM.
The reference Tenserflow Lenet code is from CarND-LeNet-Lab .
Xilinx KCU105 Board, with HDMI input and output daughter boards is used.
Connect a PC to the HDMI input daughter through a HDMI cable.
A 32x32-size input is cropped from the PC screen output, then fed into the Lenet. The classified result is displayed on the HDMI output.
The following pic is cropped from the HDMI output of FPGA. The white rectangle is draw by FPGA. Move a Mnist digit picture into the rectangle, or draw a digit by hand using a Paint software. The printed digit under the rectangle is the the classified result.
LulinChen
[email protected]