Chisel: A Modern Hardware Design Language
DataMirror.checkTypeEquivalence to actually check all fields of Bundles and Records. This may expose latent bugs in user code.https://github.com/chipsalliance/chisel/releases/latest/download/chisel-template.scala should instead use https://github.com/chipsalliance/chisel/releases/latest/download/chisel-example.scala
Full Changelog: https://github.com/chipsalliance/chisel/compare/v6.2.0...v6.3.0
suggestName API for hierarchy instances.SRAMInterface parameters publicly available (backport #3826) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3827)
memSize, dataType, numReadPorts, numWritePorts, numReadwritePorts, masked parameters are now visible for SRAMInterface.Reg() to properly handle clocks as rvalues (backport #3775) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3779)
DataView (including FlatIO)Reg()
rm -rf
--log-level to circt.stage.ChiselStage
object circt.stage.ChiselStage was ignoring the Logger.DataMirror.checkTypeEquivalence to actually check all fields of Bundles and Records. This may expose latent bugs in user code.SRAMInterface address width (backport #3830) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3839)https://github.com/chipsalliance/chisel/releases/latest/download/chisel-template.scala should instead use https://github.com/chipsalliance/chisel/releases/latest/download/chisel-example.scala
import chisel3._
import chisel3.util._
mikepenz/release-changelog-builder-action to v4.1.1Full Changelog: https://github.com/chipsalliance/chisel/compare/v5.1.0...v5.2.0
suggestName method to HasTarget (backport #3881) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3882)
HasTarget trait now also exposes suggestName method of a NamedComponent.stop is no longer ignored. The construct was extended to accept Printable.--log-level to circt.stage.ChiselStage
object circt.stage.ChiselStage was ignoring the Logger.Full Changelog: https://github.com/chipsalliance/chisel/compare/v6.1.0...v6.2.0
implicitClock and implicitReset that can be overridden within Module to change what values are used as the implicit clock and implicit reset respectively.SRAMInterface parameters publicly available (backport #3826) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3828)
memSize, dataType, numReadPorts, numWritePorts, numReadwritePorts, masked parameters are now visible for SRAMInterface.Reg() to properly handle clocks as rvalues (backport #3775) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3780)
DataView (including FlatIO)Reg()
DataMirror.isVisible and other things checking visibility now work properly for views.SRAMInterface address width (backport #3830) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3840)rm -rf
java.lang.UnsatisfiedLinkError: Error looking up function 'stat': java: undefined symbol: stat
mikepenz/release-changelog-builder-action to v4.1.1import chisel3._
import chisel3.util._
Full Changelog: https://github.com/chipsalliance/chisel/compare/v6.0.0...v6.1.0
implicitClock and implicitReset that can be overridden within Module to change what values are used as the implicit clock and implicit reset respectively.SRAMInterface parameters publicly available (by @debs-sifive in https://github.com/chipsalliance/chisel/pull/3826)
memSize, dataType, numReadPorts, numWritePorts, numReadwritePorts, masked parameters are now visible for SRAMInterface.--use-legacy-shift-right-width. Users are encouraged to generate Verilog with and without this option and diff it to ensure the width change does not affect the correctness of their design. Note that this option is purely for code migration and should not be used long term--it will eventually be removed.%.Reg() to properly handle clocks as rvalues (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3775)
DataView (including FlatIO)Reg()
DataMirror.isVisible and other things checking visibility now work properly for views.SRAMInterface address width (by @debs-sifive in https://github.com/chipsalliance/chisel/pull/3830)rm -rf
java.lang.UnsatisfiedLinkError: Error looking up function 'stat': java: undefined symbol: stat
mikepenz/release-changelog-builder-action to v4.1.1import chisel3._
import chisel3.util._
mlirBytecodeStream to PanamaCIRCT (by @SpriteOvO in https://github.com/chipsalliance/chisel/pull/3823)Full Changelog: https://github.com/chipsalliance/chisel/compare/v6.0.0...v7.0.0-M1
SRAM targets accessible from SRAMInterfaces instantiated via the SRAM object, which sets the underlying field in SRAMInterface.trait AutoCloneType (its always enabled, the trait is a no-op)chisel3.experimental.ChiselEnum (use chisel3.ChiselEnum)chisel3.experimental.EnumType (use chisel3.EnumType)chisel3.experimental.EnumType (use chisel3.reflect.DataMirror)chisel3.internal.requireIsHardware (use chisel3.experimental.requireIsHardware)chisel3.internal.requireIsChiselType (use chisel3.experimental.requireIsChiselType)chisel3.internal.sourceinfo.* (use chisel3.experimental.sourceinfo.*)chisel3.internal.prefix (use chisel3.experimental.prefix)chisel3.internal.noPrefix (use chisel3.experimental.noPrefix)chisel3.internal.ChiselException (use chisel3.ChiselException)chisel3.internal.InstanceId (use chisel3.InstanceId)trait BackendCompilationUtilities
chisel3.util.MuxLookup(key, default, mapping) (use chisel3.util.MuxLookup(key, default)(mapping), it has much better type inferencing behavior)--mlir-print-ir-after-all option. (by @poemonsense in https://github.com/chipsalliance/chisel/pull/3704)
Fix the --mlir-print-ir-after-all option.BuildInfo.firtoolVersion and will thus automatically include new releases. Versions of Chisel that predate BuildInfo.firtoolVersion are included in the table manually.<unknown>.CHISEL_FIRTOOL_PATH.Full Changelog: https://github.com/chipsalliance/chisel/compare/v6.0.0-RC1...v6.0.0-RC2
AnyRef type and rework PropertyType.getPropertyType (by @albertchen-sifive in https://github.com/chipsalliance/chisel/pull/3522)aliasName to Bundles: a way for users to define a type alias for a bundle type, resulting in the emission and usage of alias type statements in FIRRTL.HasAutoTypename traittypeName for Bundle objects through the compiler plugin.DedupGroupAnnotation phase that generates deduplication groups based on module desiredNames
:=connects for probes, which will emit a ProbeDefine.disallowIOCreation(). This is useful for building chisel libraries which desire this behavior, but don't want to force a user to declare the entire IO in one bundle.@instantiable and @pulic.dontTouch will maintain the same behavior by default by applying dontTouch to every leaf when the argument is an Aggregate. The new argument markAgg can be set to true to have dontTouch mark the Aggregate instead.clock and cond from probe force and release methods.MemoryWritePort and MemoryReadWritePort classes publicly accessible.const wires. This will facilitate further support for const in operations and the type system in the future.chirrtl.memoryport position (by @SpriteOvO in https://github.com/chipsalliance/chisel/pull/3544)simpleClassName utility object that emulates a getClass.getSimpleName call without throwing Malformed class name exceptions when Java 8 is used. typeName and all related implementations use this function now instead of getClass.getSimpleName.HasAutoTypename can no longer be mixed into an anonymous Record; the compiler plugin now reports this as a compilation error.foo and then foo_ will no longer trigger an error.Vecs, also set the probeInfo of their sample_element, which is used to determine its element type..html or .htm (remove the extension). Do this same redirect for old website /chisel3/... links as well.PanamaCIRCTConverter (by @SpriteOvO in https://github.com/chipsalliance/chisel/pull/3520)collectAlignedDeep) no longer require Data to be Hardware and may be used on bare Chisel types.Full Changelog: https://github.com/chipsalliance/chisel/compare/v6.0.0-M3...v6.0.0-RC1
CHISEL_USE_COLOR. Set to true to force Chisel to use color and false to disable it.TERM to be set to something other than dumb.SyncReadMem wrapper is instantiated using a new object, SRAM.apply, and invokes .write, .read, and .readWrite to generate a desired number of read, write, and read/write ports. This function returns a new Bundle wire containing the control signals for each requested port.SRAM.apply and SRAM.masked now take a contents parameter, by default a None, which is a string path to a binary file on the filesystem which the SRAM should be initialized with.SRAM APIs that take three Clock sequences as parameters instead of the number of read/write/read-write ports. This will sequentially instantiate a memory port for each clock in the Clock sequence and drive them accordingly.SyncReadMem.readWrite when explicit clocks are used (backport #3313) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3316)assert from an svsim simulation run may kill the simulated process before it can finish writing a waveform.stderr could hangFull Changelog: https://github.com/chipsalliance/chisel/compare/v5.0.0...v5.1.0
errorOnAsUInt to make it an elaboration time error if .asUInt is called on an instance of the particular type (including when nested inside of an Aggregate). This closes a large loophole in the OpaqueType API.SRAM.apply and SRAM.masked now take a contents parameter, by default a None, which is a string path to a binary file on the filesystem which the SRAM should be initialized with.SRAM APIs that take three Clock sequences as parameters instead of the number of read/write/read-write ports. This will sequentially instantiate a memory port for each clock in the Clock sequence and drive them accordingly.take method on Bits that returns the requested number (by @chick in https://github.com/chipsalliance/chisel/pull/3402)
take will accept an argument of zero and will return a zero-length UIntFirtoolBinaryPathOption to select a different firtool binary at runtime.Data and can only be used by simulation-only APIs.BoringUtils.bore(source, sinks), BoringUtils.addSource and BoringUtils.addSink are now deprecated in favor of the new BoringUtils APIs: BoringUtils.bore(source), BoringUtils.tap(source) ...val x = (Wire(Bool()), Wire(Bool())) will generate wires with names x_1 and x_2
stderr could hangprobe.force and probe.forceInitial methods. (by @debs-sifive in https://github.com/chipsalliance/chisel/pull/3418)
Properly extend forced values in probe.force and probe.forceInitial methods. Error out on unknown widths.: between filename and line number).CHISEL_ARGUMENT_EXTENSIONS environment variable is set to DISABLE
Full Changelog: https://github.com/chipsalliance/chisel/compare/v6.0.0-M2...v6.0.0-M3