Accelerating Quantized CNN Inference On FPGA Save
A DNN Accelerator implemented with RTL.
Project README
English | 简体中文
DNN Accelator
This repository utilizes Verilog to implement common operators in deep neural network (DNN).
Documentation
The docs have been placed in the Wiki. Please read the docs for more information.
How to Get Help
Issues can be emailed to me or left as Issues in the repository. I will reply to them as promptly as possible.
Contributor
Haisheng Zheng ([email protected])
License
Open Source Agenda is not affiliated with "Accelerating Quantized CNN Inference On FPGA" Project. README Source: CNILeo/DNN-Accelerator
Stars
58
Open Issues
0
Last Commit
10 months ago
Repository
License
Open Source Agenda Badge
