Blazing fast and correct x86/x64 disassembler, assembler, decoder, encoder for Rust, .NET, Java, Python, Lua
BlockEncoder
returning an error when trying to encode a 32-bit branch from 0
-> FFFFFF00
#511Instruction::try_immediate()
to the API docs #438 (Credit @mbbutler)AVX-VNNI-INT16
SHA512
SM3
SM4
TSE
AMX-COMPLEX
CMPccXADD
instructions #374hashbrown
dependency that was used if no_std + serde
has now been removed.RMPQUERY
AMX-FP16
AVX-IFMA
AVX-NE-CONVERT
AVX-VNNI-INT8
CMPCCXADD
MSRLIST
PREFETCHITI
RAO-INT
WRMSRNS
BlockEncoder
speed #262, #265
Decoder
speed (100MB/s -> 130MB/s, .NET 6 x64) #266, #267
XSHA512
alias #261a.zero_bytes()
) that can be used as an assembler label #272CodeAssembler::assemble_options()
and an API to get the address of labels after the code has been assembled #273PADLOCK
instructions, added missing XSHA512
instruction #260 (VIA info from @tremalrik)IsJcxShort
/IsLoopcc
/IsLoop
methods/props #227 (Credit @am0nsec), #259CodeAssembler
traits public #236 (Credit @Kixiron)Instruction
/Register
fns const
#240 (Credit @i509VCB)HashMap
(hashbrown
crate if no_std
) dependency from block_encoder
feature #248
no_std
on Windows)Instruction::with_*
methods (use with{1,2,3,4,5}()
instead)BigInt
is supported by default now #258DecoderOptions::KNC
to the Decoder
constructormvex
feature must also be enabled to decode KNC instructionsmypy
reporting errors, see here
serde
feature): json deserialization (Instruction
) is faster (json is still inefficient and slow, though)Jcc
, SETcc
, CMOVcc
, REP{,N}E
aliases (eg. a.jz(lbl)
)a.vex()
/a.evex()
fns to select VEX
or EVEX
encodinglet mut a = CodeAssembler::new(64)?;
a.xor(ecx, ecx)?;
a.add(byte_ptr(rdx + r15 * 8 + 7), 0x10)?;
assert_eq!(a.instructions().len(), 2);
let bytes = a.assemble(0x1234_5678)?;
assert_eq!(bytes, b"\x31\xC9\x42\x80\x44\xFA\x07\x10");
All instructions are supported, including VEX/EVEX instructions.
It requires the code_asm
feature which is disabled by default.
See the Rust README for a longer example.Instruction::with{1,2,3,4,5}()
methods to create instructions. The older methods with longer names have been deprecated.
// old:
let _ = Instruction::try_with_reg_reg_u32(Code::Imul_r16_rm16_imm16, Register::CX, Register::DX, 0x5AA5)?;
// new: (the '3' suffix means '3 operands')
let _ = Instruction::with3(Code::Imul_r16_rm16_imm16, Register::CX, Register::DX, 0x5AA5)?;
// A number suffix (`u32`, `u64`, `i64`) is sometimes needed to help the compiler:
let _ = Instruction::with2(Code::Mov_r64_imm64, Register::RAX, 0x1234_5678_9ABC_DEF0u64)?;
Instruction
can be serialized/deserialized with pickle
(Credit: @paulfariello)Instruction::is_string_instruction()
(Credit: @woodruffw) which returns true if it's eg. SCASB
, MOVSQ
, or any other string instruction.serde
feature added to serialize/deserialize Instruction
AVX512-FP16
instructions0F 0E
and 0F 0F
instructions (enable with DecoderOptions.Udbg/::UDBG
), see https://github.com/chip-red-pill/udbgInstr
MemoryOperand.ctor_u64()
to create an instance with an unsigned displ
Decoder
perf improvements
VPCMP{U,}{B,W,D,Q}
pseudo ops, eg. VPCMPLEB
gas
formatter updated to add SYSEXIT
L
/Q
suffixes in 64-bit mode instead of a REX.W
prefix