Deep learning toolkit-enabled VLSI placement
A High-performance Timing Analysis Tool for VLSI Systems
Standard Cell Library based Memory Compiler using FF/Latch cells
Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
A Standalone Structural Verilog Parser
VLSI EDA Global Router
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SP...
DATC RDF